• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 591 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

About srio line loopback

Yi Yin1
Intellectual 430 points
Other Parts Discussed in Thread: CDCM6208

Hi

I am debugging the SRIO between c6670 and FPGA. I have enabled  the SRIO in line loopback mode by set  PLM_SP(n)_IMP_SPEC_CTL.LLB_EN to '1'. 

But when FPGA send data to c6670, not any data come back  from C6670.(not any data be send from C6670)

Could you tell me the possible causes?

 

And I have checked the errata about srio line loopback.

http://www.ti.com/lit/er/sprz352f/sprz352f.pdf

Advisory 20 Corruption of Control Characters In SRIO Line Loopback Mode Issue

I understand that the FPGA must use the same reference clock for the SRIO physical layer.

If FPGA and C6670 use different reference clock, Could some data come back  from C6670?

Thanks,

Yin

  • 0
    TI__Mastermind 23525 points

    Since there is no clock compensation and the FIFO is very small, you have to use the same ref clock on both devices.  If not, you won't be able to send any SRIO packets or maintain port_ok at all.


    Regards,

    Travis

  • 0 in reply to tscheck
    Intellectual 430 points

    Hi Travis

    Thank you for a reply!

    I understand that it is important to use the same ref clock on both devices.

    But now, in  line loopback mode, still no any data come back  from C6670.

    And I have checked my board, the connection of  ref clock like this:

    FPGA's ref clock is from the clock generator CDCM6208's fout  pin, and the ref clock is 156.25MHz

    C6678's ref clock is also from the same CDCM6208, but using a other fout pin. and the ref is also 156.25MHz.

    According to the datasheet of CDCM620, the skew between the two fout pin is 80ps.

    My question is:

    1. On the conditions above, in srio line loopback mode,could some any SRIO packets be send?

    2 To use the srio line loopback mode  what else I need to configure besides PLM_SP(n)_IMP_SPEC_CTL.LLB_EN?

     

    Thanks,

    Yin

     

  • 0 in reply to Yi Yin1
    TI__Mastermind 23525 points

    We have not tested this capability at TI.  I would imagine that the 80ps phase offset is fine, as long as the two sources are synchronized in frequency/drift, but I am not certain.

    I don't believe anything else needs to be changed or configured to use the line loopback, but you should try to set the PE_SET_CNTL[3:0]=0b1111.  You should fully configure the SRIO and SerDes just like normal use, then enable the line loopback.  You are able to establish a link (port_ok) and transfer data between the two devices when line loopback is disable correct? 

    Regards,

    Travis