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C6457 McBSP Design Issue

  1. C6457 1GHz version McBSP max data rate 100Mbps?
  2. C6457 McBSP(1.8V IO) interface with FPGA/MCU, which is 3.3V IO, please recommend level shifter device without or minimum compromise the McBSP data rate?

Thanks.

  • Ruifeng,

    According to table 7-75 of the datasheet, the minimum cycle time for McBSP = 10P = 10ns for 1GHz device. Therefore, max freq of McBSP = 100MHz. I think you will expect to see about 75Mbps throughput at this speed.

    http://www.ti.com/lit/gpn/tms320c6457

     

    Here is a link to our Level Translation selection that should help you find a dual supply translator:

    http://focus.ti.com/logic/docs/translationselection.tsp?sectionId=458

    Aaron

  • Do you need to go 100 MHz?  I have not tested the McBSP on this specific device, but on 6455 I saw issues when going over 20 MHz because EDMA could not keep up due to transfer latency.  In other words, because the McBSP requests EDMA transfers with a size of "1 element" you lose all the bursting capabilities that have been built into EDMA, Switched Central Resource, DDR2, etc.  Once you factor other system activity into the equation (cache misses, etc.) the EDMA will end up being late, especially on the transmit side.

    Perhaps there's another interface you can use instead of McBSP or in addition.