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TMS320C6670 PLL1 init error problem

Changhee Lee
Prodigy 40 points
Other Parts Discussed in Thread: TMS320C6670

Hi,

The board which i designed has PLL1 init problem.

CCS console window show me following messages.

==============================================================

C66xx_0: GEL Output: Setup_Memory_Map...
C66xx_0: GEL Output: Setup_Memory_Map... Done.
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: C6670L GEL file Ver is 2.005
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K
C66xx_0: GEL Output: L1D = 32K
C66xx_0: GEL Output: L2 = ALL SRAM
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL in Bypass ...
C66xx_0: GEL Output: Error while waiting for GOSTAT bit returning to 0 ...
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Security Accelerator disabled!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ...
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: 2: XMC setup complete.
C66xx_0: GEL Output:
DDR3 initialization is complete.
C66xx_0: GEL Output: DDR done
C66xx_0: GEL Output: DDR3 memory test... Started
C66xx_0: GEL Output: DDR3 memory test... Failed

==============================================================

EVM(TMDXEVM6670L) has no error when i use a same gel file. But, My board is not.

I guess that it maybe the error which PLL1 doesn't set to multiplier&divider value!!

(PLL1_M=31, PLL1_D=1)

and then, PLL2 and PLL3 are well done!!

My board use LVDS 122.88MHz altcoreclk as Main PLL input, and SYSCLK_P/N are termed. and the quality of LVDS clk is good!

Differential P-P voltage is about 850~880mV and clock wave looks good. 

Device full part number is "TMS320C6670CYP 1.2GHz).

In addition, I saw amazing thing when I test my board.

When I removed the cap of altcoreclk input and then connected it by using 0 ohm resistor, (AC coupled --> DC coupled)

Error is cleared!!!

It is normally operation of  6670 DSP? 

If I use DC coupled connection of altcoreclk, the DSP of my board will be damaged? 

Please, tell me solution about this problem.

 

Thank you and best regards. 

 

  • 0
    TI__Mastermind 46460 points

    Changhee,

    The AC coupling on the clock input is needed.  It is odd that this makes a difference.

    Please verify that you are following the power - clock - reset sequencing correctly per the Data Manual.

    I assume that the GEL you are using is customized.  Why are you programming the Main PLL before the PSC enables?  You should follow the sequence in the GEL file provided with CCS and the EVM.

    Do you see this on all boards or only a few?

    Tom

     

  • 0 in reply to Tom Johnson 16214
    Prodigy 40 points

    Dear Tom,

    The AC coupling on the clock is mandatory? If I use the DC coupling on the clock, DSP clock port will be damaged?

    I think that the power-clock-reset sequence of my board is according to the Data Manual.

    (7.2.1.1 Core-Before-IO Power Sequencing, on page 111, tms320c6670 datasheet)

    * My board power-clock-reset sequence

    CVDD -> (1ms) -> CVDD1 -> (4.5ms) -> DVDD18 -> (4ms) -> DVDD15 & RESTET_N high -> (200ms)

    -> POR_N high -> (2us) -> RESETFULL_N high -> (2ms) -> RESETSTATE_N high

    I think that the power-clock-reset sequence of my board is regular operation, because the RESETSTATE_N is be changed to high. Is it right?

    And I used the GEL file which provided with the EVM.

    My board has three 6670 DPSs per a board. and PLL1 error is showed up all DSPs on all board.

    Thank you.

  • 0 in reply to Changhee Lee
    Prodigy 40 points

    Dear Tom,

    The PLL1 is operated normally.

    I changed to the power-clock-reset sequence timing, then It becomes good.

    I changed to the timing as follows :

    CVDD -> (1ms) -> CVDD1 -> (4.5ms) -> DVDD18 -> (4ms) -> DVDD15 & RESTET_N high -> (2.18s)

    -> POR_N high -> (6.25us) -> RESETFULL_N high -> (2ms) -> RESETSTATE_N high

    This sequence timing is ok ?

    I will wait for your reply.

    Thank you. 

  • 0 in reply to Changhee Lee
    TI__Mastermind 46460 points

    Changhee,

    What did you change?  The sequence appears the same.  Please verfify the rise time of these supplies.  The sequencing is measured from the time the previous supply reaches a valid level to the start of the next supply.

    Tom