Hi,
I have a custom board having 2 C6678s on it. I try to use SRIO between them. The reference clock value for both of them is 250Mhz. So due to the post "http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/127613/476981.aspx#476981" the serdes settings should be as following:
For the C6670 EVM the reference clock is 250Mhz. So the settings would be:
CSL_BootCfgSetSRIOSERDESConfigPLL (0x065);
CSL_BootCfgSetSRIOSERDESRxConfig (0, 0x004404a5);
CSL_BootCfgSetSRIOSERDESTxConfig (0, 0x001807a5);
Here these values for C6670, but I suppose that this is the same for C6678.
Q1. Form the value of configPLL, the MPY value =00110010. But this value is seemed to be inaccurate according to SRIO UG table.3.7.
Q2. By using these values, I observed that link is established and I can send messages over SRIO. When I check the ERR_STAT registers for the ports, some ports are seemed to be not PortOK (ERR_STAT=0x30305 or 0x30301). Is it possible that some of the ports does not work? Which registers gives the information about link status?
Q3. Can I select the port to which I send the messages?
Thank you,
Alpaslan