Test L2 ECC error handling

this document may help.

Thanks, although it doesn't look like that applies to the Sitara Cortex-A8?

Yes RKU, that l link was just for reference manual about ecc. Ti developed ECC generation tool for micro-controller family as nowecc. You can also take a reference of NAND ECC Generation for DaVinci Family of Devices to manually generate an L2 ECC.

Best luck.

RKU,

I'm not aware of any method for intentionally injecting errors into the L1 or L2 of the Cortex A8.  Since the cache is not memory mapped there's no way to access it.  I've emailed ARM to see if they have any additional comments, i.e. a backdoor method or something.  I'll follow-up with their response.

Brad