Hi,
I have a small LCD that needs 6.75MHz VCLK output along with HD and VD outputs plus RGB outputs.
I have settings for all the VENC registers that get me to a 13.5MHz clock.
Describing the problem is not helped by the fact that there are two registers with very similar names!
VPSS_CLK_CTRL is described in SPRUFB3A and enables/disables the VENC_CLK as well as configuring its source.
I have managed to make this work correctly and can select either the 27MHz MXI2/MXO2 or the 13.5MHZ SYSCLK3 (= PLL1/32)
The problem is with VPSS CLKCTRL as described in SPRUF71A. This register appears to also gate the VPBE_CLK and allows for dividing that clock by two using VENC_CLKSEL.
What I have found is that whenever I write 1 to the VENC_CLKSEL field the VENC stops producing an output clock.
I have tried gating the clock at VPSS_CLK_CTRL prior to changing this register, then re-enabling it, but it doesn't help.
Am I misinterpreting the purpose of the enc_clk/2 setting? Do I need to approach this differently?
All help appreciated ...
// Edited to correct required output clock frequency.