PCIE inbound memory access

Paul,

Please refer to working example code and document here:

C:\ti\MCSDK_02_01_02_06\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie

C:\ti\MCSDK_02_01_02_06\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\docs\README.pdf

regards,

David

David,

The examples you are referring to, shows how to use PCIe. However, it is assumed that PCIE is initialized already. And it is, when we are using PCIe boot scenario. In my case the application wil be stored in NOR flash and EMI boot procedurę will be there. That's why I have to set up PCIe from the scratch on my own. I know it looks weird, as thanks to PCIe boot I don't need parallel FLASH memory. So let me explain - that's for security reasons. DSP code must NOT be accessible from host machine. Only shared memory window will be visible to both parties. To do this, MPU will be used.

Going back to the topic. I found promising initialization procedurę in PDK example - c:\ti\pdk_c6678_1_1_2_6\packages\ti\drv\pcie\example. Why promising? From the beginning it seems to be OK, as the board gets enumerated within PC and operating system properly reports PCI BARs exposed. However, upstairs begins when I am going to touch DSP memory from PC - problem described in my first post occurs.

Paul

UPDATE: I found another initialization example in C:\ti\mcsdk_2_01_02_06\tools\boot_loader\ibl\src\device\c66x\c66xinit.c. Will check if this one works better...

Paul,

Basically the PCIe PDK/LLD example should be fine for the PCIe initialization. If you could get link up between Host PC and C6678 PCIe, the correct IB/BAR setup should allow Host to access DSP memory via PCIe link.

Are you able to dump the PCIe configuration registers (from 0x21800000) in both cases (PCIe bootloader vs PCIe PDK/LLD example) please?

We could take a look at the differences after your host PC driver configures the C6678 PCIe in both cases.

Hi,

After more tests and experiments I found that complete TI examples and my code works well when launched just after POR. But after host machine (PC computer containing TMDSEVM320C6678 module) reboot, PCIe goes into weird state. It seems that PCIe recognises host reset properly (handler for LINK_RST_REQ is called), but further access to memory BARs (1..5) doesn't work. Could you please tell me if any special action except link training is required after LINK_RST_REQ takes place?

Paul

UPDATE: I made simple workaround which seems to be working - after link reset is received, software shuts down PCIe power and turns back on a while later, before link training. However there is a garbage inside PCIe registers instead of default values, so I have to fill them manually.

One more UPDATE:

The garbage mentioned concerns VID / PID values. According to errata document (usage note "PCIe Device ID Field Reset Value"), this is expected behavior.