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Question about OMAP4470 Pad configuration tool (ball#AF21) McSPI4_SOMI

rperezti
Genius 12670 points

I'm using OMAP4470 pad configuration tool v1.3. Why does the tool lock the configuration of ball#AF21 so that it cannot be changed?  This pin shows up in yellow in the main view and all selectable options for it in the controller view are locked.

  • 0
    TI__Guru**** 161600 points

    Hello,

    I think this is a bug in PCT. According to both OMAP4470 TRM & Data Manual the following signals are multiplexed on ball AF21 (see CONTROL_CORE_PAD0_MCSPI4_SOMI_PAD1_MCSPI4_CS0[2:0] MCSPI4_SOMI_MUXMODE bit field in OMAP4470 TRM, Control Module Chapter):
    mcspi4_somi , when bit field set to mux mode 0x0

    sdmmc4_dat0, when bit field set to mux mode 0x1

    kpd_row6, when bit field set to mux mode 0x2

    gpio_153, when bit field set to 0x3

    safe_mode, when bit field set to 0x7

    I will check that with the team that supports PCT, but it's most likely a bug in the tool.

    Best Regards,

    Yordan

  • 0 in reply to Yordan Kovachev
    TI__Guru**** 161600 points

    Hi,

    As I said this is a bug in PCT. Since there is no plan to release a new version of this software any time soon, here is what you can try to fix this:

    1. In a text editor open: <install Dir>\TI_Pad_Conf_Tool\PCT-OMAP4470ES1.0-v1.3.0.0\XMLFiles\model_OMAP4470_ES1.0_v1.0.0

    2. Locate the following section:
     

    <clockNode>
     <name>mcspi4_somi</name>
      <type>
        <pad>
          <numberOfMuxmodes>8</numberOfMuxmodes>
          <muxmode>
            <mode>0</mode>
            <signal>mcspi4_somi</signal>
            <color>0xFFFF66</color>
          </muxmode>
          <muxmode>
            <mode>1</mode>
            <signal>sdmmc4_dat0</signal>
            <color>0x33FFFF</color>
          </muxmode>
          <muxmode>
            <mode>2</mode>
            <signal>kpd_row6</signal>
            <color>0x1100</color>
          </muxmode>
          <muxmode>
            <mode>3</mode>
            <signal>gpio_153</signal>
            <color>0x1100</color>
          </muxmode>
          <muxmode>
            <mode>7</mode>
            <signal>safe_mode</signal>
            <color>0x3300</color>
          </muxmode>
          <confregisters>
             <regbit>
              <register>CONTROL_CORE_PADCONF_MODE</register>
              <bitfield>VDDS_DV_BANK5</bitfield>
            </regbit>
             <regbit>
              <register>CONTROL_SMART3IO_PADCONF_0</register>
              <bitfield>MCSPI4_DR0_MB</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_SMART3IO_PADCONF_2</register>
              <bitfield>MCSPI4_DR0_LB</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_CLK_PAD1_MCSPI4_SIMO</register>
              <bitfield>MCSPI4_SOMI_WAKEUPENABLE</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_CLK_PAD1_MCSPI4_SIMO</register>
              <bitfield>MCSPI4_SOMI_OFFMODEPULLTYPESELECT</bitfield>
            </regbit>
             <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_CLK_PAD1_MCSPI4_SIMO</register>
              <bitfield>MCSPI4_SOMI_OFFMODEPULLUDENABLE</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_CLK_PAD1_MCSPI4_SIMO</register>
              <bitfield>MCSPI4_SOMI_OFFMODEOUTVALUE</bitfield>
            </regbit>
             <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_CLK_PAD1_MCSPI4_SIMO</register>
              <bitfield>MCSPI4_SOMI_OFFMODEOUTENABLE</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_CLK_PAD1_MCSPI4_SIMO</register>
              <bitfield>MCSPI4_SOMI_OFFMODEENABLE</bitfield>
            </regbit>
                    <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_CLK_PAD1_MCSPI4_SIMO</register>
              <bitfield>MCSPI4_SOMI_INPUTENABLE</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_CLK_PAD1_MCSPI4_SIMO</register>
              <bitfield>MCSPI4_SOMI_PULLTYPESELECT</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_CLK_PAD1_MCSPI4_SIMO</register>
              <bitfield>MCSPI4_SOMI_PULLUDENABLE</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_CLK_PAD1_MCSPI4_SIMO</register>
              <bitfield>MCSPI4_SOMI_MUXMODE</bitfield>
            </regbit>
          </confregisters>
          <ballname>AF21</ballname>
        </pad>
      </type>
    </clockNode>

    3. Replace the above with:

    <clockNode>
      <name>mcspi4_somi</name>
      <type>
        <pad>
          <numberOfMuxmodes>8</numberOfMuxmodes>
          <muxmode>
            <mode>0</mode>
            <signal>mcspi4_somi</signal>
            <color>0xFFFF66</color>
          </muxmode>
          <muxmode>
            <mode>1</mode>
            <signal>sdmmc4_dat0</signal>
            <color>0x33FFFF</color>
          </muxmode>
          <muxmode>
            <mode>2</mode>
            <signal>kpd_row6</signal>
            <color>0x1100</color>
          </muxmode>
          <muxmode>
            <mode>3</mode>
            <signal>gpio_153</signal>
            <color>0x1100</color>
          </muxmode>
          <muxmode>
            <mode>7</mode>
            <signal>safe_mode</signal>
            <color>0x3300</color>
          </muxmode>
          <confregisters>
             <regbit>
              <register>CONTROL_CORE_PADCONF_MODE</register>
              <bitfield>VDDS_DV_BANK5</bitfield>
            </regbit>
             <regbit>
              <register>CONTROL_SMART3IO_PADCONF_0</register>
              <bitfield>MCSPI4_DR0_MB</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_SMART3IO_PADCONF_2</register>
              <bitfield>MCSPI4_DR0_LB</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_SOMI_PAD1_MCSPI4_CS0</register>
              <bitfield>MCSPI4_SOMI_WAKEUPENABLE</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_SOMI_PAD1_MCSPI4_CS0</register>
              <bitfield>MCSPI4_SOMI_OFFMODEPULLTYPESELECT</bitfield>
            </regbit>
             <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_SOMI_PAD1_MCSPI4_CS0</register>
              <bitfield>MCSPI4_SOMI_OFFMODEPULLUDENABLE</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_SOMI_PAD1_MCSPI4_CS0</register>
              <bitfield>MCSPI4_SOMI_OFFMODEOUTVALUE</bitfield>
            </regbit>
             <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_SOMI_PAD1_MCSPI4_CS0</register>
              <bitfield>MCSPI4_SOMI_OFFMODEOUTENABLE</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_SOMI_PAD1_MCSPI4_CS0</register>
              <bitfield>MCSPI4_SOMI_OFFMODEENABLE</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_SOMI_PAD1_MCSPI4_CS0</register>
              <bitfield>MCSPI4_SOMI_INPUTENABLE</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_SOMI_PAD1_MCSPI4_CS0</register>
              <bitfield>MCSPI4_SOMI_PULLTYPESELECT</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_SOMI_PAD1_MCSPI4_CS0</register>
              <bitfield>MCSPI4_SOMI_PULLUDENABLE</bitfield>
            </regbit>
            <regbit>
              <register>CONTROL_CORE_PAD0_MCSPI4_SOMI_PAD1_MCSPI4_CS0</register>
              <bitfield>MCSPI4_SOMI_MUXMODE</bitfield>
            </regbit>
          </confregisters>
          <ballname>AF21</ballname>
        </pad>
      </type>
    </clockNode>


    Hope this is helpful.

    Best Regards,

    Yordan