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Our MLO doesn't work as same as Starterware MLO

Hi,

I've been working on Starterware applications for a while on the TI AM335X (General Purpose) EVM. The standalone  media (MMCSD card) booting is successful with MLO and app files. 

I think it's a good way to test/debug hardware without the need of booting up the whole system.

Now I want our board (which is designed based on this TI AM335X (General Purpose) EVM but has DDR3 used and other minor changes) to run an application on a standalone MMCSD card also with just MLO and app files. It doesn't work!

Here is how I make it---

1. I select one application that works good with CCS and debuging tools on our board, the result shows up in our serial port terminal just as expected. So I make the app file following http://processors.wiki.ti.com/index.php/AM335X_StarterWare_Booting_And_Flashing#Usage_of_ti_image_Tool

2. Find the MLO file that we're using to boot regular file system. The boot files we have for booting our board includes 4 files: MLO, u-boot.img, uEnv.txt, uImage.

3. Then I flash the MLO with the app file into a MMCSD card and try to boot the board just from it, there's nothing show up...it's dead seems.

Can anybody let me know what's the issue is and what I can do?

Thanks,

Susan 

 

  • Hi !!

    "Now I want our board " U mean u are trying to bring up a customised board. If its a customised board i would suggest to go for peripheral booting i.e UART. as the hardware complexity is very less as compared to SD card. i have shared the binaries http://e2e.ti.com/support/embedded/starterware/f/790/t/317144.aspx . Most probably u have to sure that the boot pin configuration is fine. ti MLO does not include changes for DDR3. if u have not made changes for DDR3 please refer this Link http://e2e.ti.com/support/embedded/starterware/f/790/t/271176.aspx . the three files here shared are needed to be added in the project and u need recompile and make a customised MLO. if every thing is right with the customised board hardware wise u will be able to boot.

  • Hi,

    Thank you for the answer.

    I do mean working on a customised board. We have DDR3 and 512M nand Flash on it. I've tried both the binary and the 3 files in the link, none of them works yet... 

    The example you gave is on beaglebone board, do you think it's the same on a design based on AM335x GP board?

    More suggestion is highly appreciated! 

  • Hi,

    I'm still not successful...can you or anyone help me further by checking the modification in below? Is more modification required?

    1.Modify bl_platform.h for the 512M nand Flash:

    #define NAND_NUMOF_BLK (4096)//original 2048 in file

    #define NAND_DEVICE_ID (0xDC)//original DA

    2. Modify bl_platform.c for our DDR3:

    #include "pin_mux.h" //under AM335x option

    #define DDR3_DATA0_WR_DQS_SLAVE_RATIO_0 (0xAB)//original 3C

    #define DDR3_DATA0_FIFO_WE_SLAVE_RATIO_0 (0x108)//original A5

    #define DDR3_DATA0_WR_DATA_SLAVE_RATIO_0 (0xE3)//original 74

    #define DDR3_DATA0_WR_DQS_SLAVE_RATIO_1 (0xAB)//original 3C in file

    #define DDR3_DATA0_FIFO_WE_SLAVE_RATIO_1 (0x108)//original A5

    #define DDR3_DATA0_WR_DATA_SLAVE_RATIO_1 (0xE3)//original 74

    #define DDR3_EMIF_SDRAM_CONFIG (0x61C04AB2) //original ...BB2

    Above is refer to our customised board working .gel file:

    #define DATA_PHY_RD_DQS_SLAVE_RATIO 0x3B

    #define DATA_PHY_FIFO_WE_SLAVE_RATIO 0x108 //RD DQS GATE

    #define DATA_PHY_WR_DQS_SLAVE_RATIO 0xAB

    #define DATA_PHY_WR_DATA_SLAVE_RATIO 0xE3 //WRITE DATA

    #define DDR_IOCTRL_VALUE (0x18B)

    //******************************************************************

    //EMIF parameters

    //******************************************************************

    #define ALLOPP_DDR3_READ_LATENCY 0x06 //RD_Latency = (CL + 2) - 1

    #define ALLOPP_DDR3_SDRAM_TIMING1 0x0888A39B

    #define ALLOPP_DDR3_SDRAM_TIMING2 0x26337FDA

    #define ALLOPP_DDR3_SDRAM_TIMING3 0x501F830F

    #define ALLOPP_DDR3_SDRAM_CONFIG 0x61C04AB2 //termination = 1 (RZQ/4)

    //dynamic ODT = 2 (RZQ/2)

    //SDRAM drive = 0 (RZQ/6)

    //CWL = 0 (CAS write latency = 5)

    //CL = 2 (CAS latency = 5)

    //ROWSIZE = 5 (14 row bits)

    //PAGESIZE = 2 (10 column bits)

  • Hi,

    In StarterWare release Beaglebone is configured for  DDR2. Please check if the necessary migration (of VTT Enable, DDR3Init) from DDR to DDR3 is taken care. And also check if all EMIF macros match that of working gel file.

    Regards,

    Ramesh D