AM335x minimum clocking speed

Biser,

I've read section 8.16 and subsections again ( and the linux page ) but I don't see where it tells me what I can safely turn the clock down to.....

Regards

Paul.

Which clocks are you asking about?

I'm interested in the minimum operating range of the processor Core,  ARM subsystem and DDR primarily. 

Paul.

Biser,

Where about's it that defined? 

For instance in the DS section 3.2 and specifically table 3.2 have a footnote (1) that states the frequencies in the table indicate the maximum performance for a given OPP condition. 

We will be using the Ethernet MAC so lets ignore the core domain for now.

What is the limiting factor on the minimum operating frequency with respect to the MPU OPP. My understanding is that the OPP is simply defining the voltage applied to the silicon, higher voltage = faster operation, lower voltage = lower power consumption. I can't see then what would stop me running the device in Turbo mode if I so wished but clock at 50MHz?

I am assuming that the MPU to CORE domain crossing is taken care of?

Obviously a silly example but demonstrates the point I hope,

I'm not one for asking loads of questions but this bit of the device isn't documented very well really.

Thanks for you help.

I will add a few additional comments related to your question.

You are correct, the MPU/CORE boundary crossing was considered during AM335x design.  The design was validated based on use cases that represent how most customers planned to use the device.  We expected most customers to be running a high level OS like Linux which requires a minimum level of MPU throughput to maintain proper operation.  The minimum performance level required to support this requirement is very subjective based on many system variables.  OPP50 was defined and validated to provide customers a lower performance and lower power consumption OPP option.

The MPU can be operated at the frequency defined by OPP50 while the MPU power supply is between the minimum voltage defined by OPP50 and maximum voltage defined by the highest OPP supported by the specific AM335x device.  Reducing the MPU voltage to the lower end of this range while operating at the OPP50 frequency can significantly reduce power consumption, but lowering the MPU voltage is not required if the system can meet the AM335x thermal requirements.    

The design was not formally validated with MPU operating at very low frequencies (below the frequency defined by OPP50) and there may be unexpected limitations outside of this expected use case.  For example, all signals crossing the MPU/CORE boundary must be synchronized as they cross from one clock domain to the other clock domain.  If MPU is operated at a very low frequency relative to the CORE operating frequency, it may not detect transitions on signals with short pulses originated by the higher frequency CORE domain.

We have seen reports of some customers successfully lowering the MPU operating frequency down to a few MHz while still running Linux.  This type of simple functional test may not represent all corner cases that could occur in a real world system.   It is difficult enough to determine the minimum MPU throughput required for a high level OS without taking additional risk of operating hardware outside of the expected use case that was validated by the design team.

This is why Biser has recommended using OPP50 as your minimum MPU operating frequency.  Since your application requires OPP100 for the CORE, you may not achieve significant power savings by reducing the MPU operating frequency below OPP50 and you run the risk of not having enough MPU throughput to run your application.

Regards,
Paul

I sent an email to the design team asking them to confirm the minimum MPU operating frequency that was formally verified.

I will update this post when the design team answers this question.  However, it may take a few days to get an answer.

Regards,
Paul

Hey I saw your post say you would update this page. I do not want to start a new thread because this question is the exact same as mine.

Did the design team ever give a minimum number?

Thanks,

Evan

No afraid not and I changed processors (for reasons partly based on the answer from peaves) so never had need to chase it.

Regards

The initial answer Biser and I provided was based on early inquires that had not been confirmed by design.  Later we received confirmation the processor was able to operate with the MPU PLL in bypass mode.  Therefore, the answer we provided was not correct.

I'm sorry we never updated the post and you were required to select another processor.

Regards,
Paul 

So I'm interested in this too but I don't quite get what your final answer is? I'd like to be able to reduce power while in an idle state but maintain Ethernet functionality. The TRM states that Ethernet will not function at Core OPP50 but it wasn't clear to me about running at Core OPP100 and MPU OPP50 and what the effect would be. 

Can you elaborate on your answer? 

Thanks,
Matt S.