I have a C6748 application that uses McASP0 to interface with an I2S DAC. Recently I switched the output sampling rate from 192ksps to 384ksps. Although I do not see significant benefit in using DMA, I do see a definite advantage to using the McASP0 WFIFO to reduce the CPU interrupt rate. Since I am currently using only 1 serializer (WNUMDMA=1) in McASP0, it appears that I should be able to set WNUMEVT to any value from 1 to 64.
My original McASP0 configuration (without the WFIFO) works fine, but my WFIFOCTL configuration is not producing the expected behavior. When we wrote the original code to configure McASP0 we used macros from the Chip Support Library and we configured the needed registers “field-by-field” (using the register maps in “spruh79a.pdf”) to come up with a configuration that served our needs. Here is the core of the original configuration, with XBUSEL changed from VBUSP to VBUS, along with the addition of the WFIFO configuration:
// XFMT
CSL_FMKT(MCASP_XFMT_XDATDLY, 1BIT) // Transmit sync bit delay
| CSL_FMKT(MCASP_XFMT_XRVRS, MSBFIRST) // Transmit serial bitstream order
| CSL_FMKT(MCASP_XFMT_XPAD, ZERO) // Pad value for extra bits in slot not
// belonging to word defined by XMASK
| CSL_FMK(MCASP_XFMT_XPBIT, 0) // XPBIT value determines which bit is
// used to pad the extra bits before shifting
| CSL_FMKT(MCASP_XFMT_XSSZ, 32BITS) // Transmit slot size
| CSL_FMKT(MCASP_XFMT_XBUSEL, VBUS) // Selects whether writes to serializer buffer
// XRBUF[n] originate from the peripheral
// configuration port or the DMA port
| CSL_FMKT(MCASP_XFMT_XROT, NONE), // Right-rotation value for transmit rotate
// right format unit
// AFSXCTL
CSL_FMKT(MCASP_AFSXCTL_XMOD, I2S) // Transmit frame sync mode select
| CSL_FMKT(MCASP_AFSXCTL_FXWID, WORD) // Transmit frame sync width select
| CSL_FMKT(MCASP_AFSXCTL_FSXM, INTERNAL) // Transmit frame sync generation select
| CSL_FMKT(MCASP_AFSXCTL_FSXP, RISINGEDGE), // Transmit frame sync polarity select
// ACLKXCTL
CSL_FMKT( MCASP_ACLKXCTL_CLKXP, RISINGEDGE) // Transmit bitstream clock polarity select
| CSL_FMKT(MCASP_ACLKXCTL_ASYNC, ASYNC) // Transmit/receive operation asynchronous enable
| CSL_FMKT(MCASP_ACLKXCTL_CLKXM, INTERNAL) // Transmit bit clock source
| CSL_FMK(MCASP_ACLKXCTL_CLKXDIV, CLKXDIV_VAL), // Transmit bit clock divide ratio, divide by
// CLKXDIV_VAL+1
// AHCLKXCTL
CSL_FMKT( MCASP_AHCLKXCTL_HCLKXM, INTERNAL) // Transmit high-frequency clock source bit
| CSL_FMKT( MCASP_AHCLKXCTL_HCLKXP, NOTINVERTED) // Transmit bitstream high-frequency clock
// polarity select bit
| CSL_FMK( MCASP_AHCLKXCTL_HCLKXDIV, 0), // Transmit high-frequency clock divide
// ratio - divide by 1
// XTDM
CSL_FMKT( MCASP_XTDM_XTDMS0, ACTIVE) // Transmitter mode during TDM time slot n
| CSL_FMKT( MCASP_XTDM_XTDMS1, ACTIVE),
// XINTCTL
CSL_FMKT( MCASP_XINTCTL_XDATA, ENABLE), // Transmit data ready interrupt enable
// WFIFOCTL
CSL_FMKT(AFIFO_WFIFOCTL_WENA, DISABLED) // WFIFO disabled during config
| CSL_FMKT(AFIFO_WFIFOCTL_WNUMDMA, 1WORDS) // 1 word to McASP from FIFO
// | CSL_FMKT(AFIFO_WFIFOCTL_WNUMEVT, 32WORDS), // 32 words from CPU to FIFO per INT
| CSL_FMK(AFIFO_WFIFOCTL_WNUMEVT, 1), // 1 words from CPU to FIFO per INT
For port configuration and startup, I followed the sequence shown in Section 23.2.4.1.2 of “spruh79a.pdf”. After setting the above WFIFOCTL fields, I then switched WENA from "DISABLED" to "ENABLED".
One thing that would potentially help out would be to see a real working McASP WFIFO ISR to make sure that I am properly clearing event flags etc. in my ISR. I am becoming doubtful that I am even using the correct EVT for the WFIFO. I am actually using McASP0 on this part and I am triggering on EVT #61 in Table 5-6 of the C6748 data sheet. My impression was that the WFIFO would service the McASP0 Tx events and trigger EVT #61 when it was sufficiently drained. I am now believing that this may have been a wrong impression. No matter what level I choose for the WFIFO event, I am getting interrupted when WFIFOSTS = 63 (ie. every time the McASP transmits 1 sample), making me suspect that I am triggering on the wrong EVT. The only problem is that I can see no other good candidate EVTs in the data sheet.
Perhaps I have misinterpreted the following from Table 23-48 of “spruh79a.pdf”:
When the Write FIFO has space for at least WNUMEVT words of data, then an AXEVT (transmit DMA event) is generated to the host/DMA controller.
