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Working with EDMA3_1

Other Parts Discussed in Thread: OMAPL138

Hello,

I'm trying to work with EDMA3_1 CC instead of EDMA3_0 CC for UartDma.

EDMA3_0 works fine, I need EDMA3_1 because I believe that one channel can't support 2 UARTS.

I use Omap L138 and use SysBios6.

I've done the same initialization process that I did with the EDMA3_0, registered on interrupts 93&94 but the interrupts arn't fired, here is the code:

/*
 ** This function allocates EDMA3 channels to SPI1 for trasmisssion and
 ** reception purposes.
 */
void RequestEDMA3Channels(void)
{
	EDMA3RequestChannel(SOC_EDMA31CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
			LEFT_SENSOR_CHA, LEFT_SENSOR_CHA,
			EVT_QUEUE_NUM);

	EDMA3RequestChannel(SOC_EDMA31CC_0_REGS, EDMA3_CHANNEL_TYPE_DMA,
			RIGHT_SENSOR_CHA, RIGHT_SENSOR_CHA,
			EVT_QUEUE_NUM);
}

void EDMA3Initialize(void)
{
	/* Enabling the PSC for EDMA3CC_0.*/
	PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_CC0, PSC_POWERDOMAIN_ALWAYS_ON,
			PSC_MDCTL_NEXT_ENABLE);

	/* Enabling the PSC for EDMA3TC_0.*/
	PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_TC0, PSC_POWERDOMAIN_ALWAYS_ON,
			PSC_MDCTL_NEXT_ENABLE);

	/* Initialization of EDMA3 */
	EDMA3Init(SOC_EDMA31CC_0_REGS, 0);
	EDMA3Init(SOC_EDMA31CC_0_REGS, 0);
}
/* Invoke Completion Handler ISR */
void Edma31ComplHandlerIsr(void)
{
	volatile unsigned int pendingIrqs;
	volatile unsigned int isIPR = 0;

	volatile unsigned int indexl;
	volatile unsigned int Cnt = 0;
	indexl = 1;
	IntSystemStatusClear(SYS_INT_CCINT0);
	isIPR = EDMA3GetIntrStatus(SOC_EDMA31CC_0_REGS);
	if(isIPR)
	{
		while ((Cnt < EDMA3CC_COMPL_HANDLER_RETRY_COUNT)&& (indexl != 0))
		{
			indexl = 0;
			pendingIrqs = EDMA3GetIntrStatus(SOC_EDMA31CC_0_REGS);
			while (pendingIrqs)
			{
				if((pendingIrqs & 1) == TRUE)
				{
					/**
					 * If the user has not given any callback function
					 * while requesting the TCC, its TCC specific bit
					 * in the IPR register will NOT be cleared.
					 */
					/* Here write to ICR to clear the corresponding IPR bits. */
					EDMA3ClrIntr(SOC_EDMA31CC_0_REGS, indexl);
					if(indexl == LEFT_SENSOR_CHA)
					{
						UARTDMADisable(LEFT_SENSOR_UART, (UART_RX_TRIG_LEVEL_1 | UART_FIFO_MODE));
						SetupNextParam(indexl,EDMA3_XFER_COMPLETE);
					}
					else if (indexl == RIGHT_SENSOR_CHA)
					{
						UARTDMADisable(RIGHT_SENSOR_UART, (UART_RX_TRIG_LEVEL_1 | UART_FIFO_MODE));
						SetupNextParam(indexl,EDMA3_XFER_COMPLETE);
					}
					else
						irqRaised=1;

				}
				++indexl;
				pendingIrqs >>= 1;
			}
			Cnt++;
		}
	}
}

void RecieveData(unsigned int ulBase,unsigned int chNum,volatile char *buffer,int size){
	/* Receive Data for Input */
	EDMA3CCPaRAMEntry paramSet;
	unsigned int baseAdd;

	if(chNum == LEFT_SENSOR_CHA)
	{
		baseAdd = SOC_EDMA31CC_0_REGS;
	}
	else if(chNum == RIGHT_SENSOR_CHA)
	{
		baseAdd = SOC_EDMA31CC_0_REGS;
	}

	/* Write to EMCR to clear the corresponding EMR bits.*/
	if(HWREG(baseAdd + EDMA3CC_EMR)!=0)
	{
		HWREG(baseAdd + EDMA3CC_EMCR) = (1<<chNum);
	}
	else if(HWREG(baseAdd + EDMA3CC_SER)!=0)
	{
		HWREG(baseAdd + EDMA3CC_SECR) = (1<<chNum);
	}

	/* Fill the PaRAM Set with transfer specific information */
	paramSet.srcAddr = ulBase;
	paramSet.destAddr = (unsigned int) buffer;
	paramSet.aCnt = 1;
	paramSet.bCnt = size;
	paramSet.cCnt = 1;

	/* The src index should not be increment since it is a h/w register*/
	paramSet.srcBIdx = 0;
	/* The dest index should incremented for every byte */
	paramSet.destBIdx = 1;

	/* A sync Transfer Mode */
	paramSet.srcCIdx = 0;
	paramSet.destCIdx = 0;
	paramSet.linkAddr = (unsigned short)0xFFFFu;
	paramSet.bCntReload = 0;
	paramSet.opt = 0x00000000u;
    //paramSet.opt |= ((EDMA3CC_OPT_SAM) << EDMA3CC_OPT_SAM_SHIFT);
	paramSet.opt |= ((chNum << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
	paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);

	/* Now write the PaRAM Set */
	EDMA3SetPaRAM(baseAdd, chNum, &paramSet);

	/* Enable EDMA Transfer */
	EDMA3EnableTransfer(baseAdd, chNum, EDMA3_TRIG_MODE_EVENT);

	/* Enabling UART in DMA Mode*/
	UARTDMAEnable(ulBase, UART_RX_TRIG_LEVEL_1 | \
			UART_DMAMODE |         \
			UART_FIFO_MODE );
}

Do I miss something in the initialization process?
Where can I find any information about working with those channels?

Thanks,
Yoel

  • Hi Yoel,

    Thanks for your post.

    I don't think, we have sample examples in starterware as well bios using EDMA3_1 channel TC's & CC's. But we do have a scenario in an E2E thread below, using two DMA channels in parallel, the first dma channel using SPI DAC and the second channel used for data copy from SDRAM. Also, there is a TI wiki article which gives you an overview of EDMA3_1 TC0 read accesses from SRC peripheral and write accesses to DST peripheral. Please walkthrough SRC peripheral and default burst size in the wiki article mentioned below:

    http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/106692.aspx

    http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_SoC_Architectural_Overview#Switched_Central_Resource_.28SCR.29

    Additionally, inorder to validate the connection between masters and slave, each master request source must have a unique master ID (mstid) associated with it. Please refer Section 11.3 in the omapl138 TRM as well Table 11-1 and Table 11-2 for default priority levels for each bus master and ensure the proper mapping of master id's for EDMA3_1_TC0 read and write requests from masters prioritized by each SCR

    http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf

    Thanks & regards,

    Sivaraj K

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