This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC with AM335x PRUSS

I am trying to use the ADC module from an assembly program running in the PRU, but I've got an infinite loop as pointed in the code below. I would like to know if I forgot to enable interrupts somehow, and how would it be possible to sample signals using the PRU. (My platform is a BeagleBone Black).

Thanks in advance.

CODE:

// testADCPRU2.p

 

.origin 0

.entrypoint CONFIGURE

 

#define ADC_TSC_REGISTERS_BASE 0x44E0D000

#define STEPCONFIG1_OFFSET 0x64

#define STEPDELAY1_OFFSET 0x68

#define STEPENABLE_OFFSET 0x54

#define IRQENABLE_SET_OFFSET 0x2C

#define IRQSTATUS_OFFSET 0x28

#define CTRL_OFFSET 0x40

#define FIFO0THRESHOLD_OFFSET 0xE8

#define FIFO0DATA_OFFSET 0x100

 

#define CONST_PRUCFG C4

 

#include "testADCPRU2.hp"

 

CONFIGURE:

 

                   // Clear syscfg[standby_init] to enable ocp master port

                   // spruhf8 AM335x PRU-ICSS Reference Guide 11.1.2

                   LBCO    r0, CONST_PRUCFG, 4, 4

                   CLR     r0, r0, 4

                   SBCO    r0, CONST_PRUCFG, 4, 4

                  

 

                   //R1 --> STEPCONFIG1

                   MOV32        R1, ADC_TSC_REGISTERS_BASE + STEPCONFIG1_OFFSET

                   MOV32        R2, 0x00000000

                  

                   //STEPCONFIG1 = 0x00000000

                   SBBO  R2, R1, 0, 4

                  

                   //R1 --> STEPDELAY1

                   MOV          R1, ADC_TSC_REGISTERS_BASE + STEPDELAY1_OFFSET

                   MOV          R2, 0x00005DC0    

                   //STEPDELAY1 = 0x00005DC0 (open delay of 24000 cycles = 1 ms)

                   SBBO  R2, R1, 0, 4

            

                   //R1 --> STEPENABLE

                   MOV          R1, ADC_TSC_REGISTERS_BASE + STEPENABLE_OFFSET

                   MOV          R2, 0x00000002

                   //STEPENABLE = 0x00000002 (enable step 1)

                   SBBO  R2, R1, 0, 4

                  

                   //enable fifo0_threshold interrupt

                   //R1 --> IRQENABLE_SET

                   MOV          R1, ADC_TSC_REGISTERS_BASE + IRQENABLE_SET_OFFSET

                   MOV          R2, 0x00000004

                   SBBO  R2, R1, 0, 4

                  

                   //1 sample limit

                   //R1 --> FIFO0THRESHOLD

                   MOV          R1, ADC_TSC_REGISTERS_BASE + FIFO0THRESHOLD_OFFSET

                   MOV          R2, 0x00000000

                   SBBO  R2, R1, 0, 4

                  

TESTPRU:

 

                   //R3: POINTER TO REGISTER IRQSTATUS

                   MOV          R3, ADC_TSC_REGISTERS_BASE + IRQSTATUS_OFFSET

 

                   //R4: POINTER TO REGISTER FIFO0DATA

                   MOV          R4, ADC_TSC_REGISTERS_BASE + FIFO0DATA_OFFSET

                  

                   //enable step_ID_tag, enable TSC_ADC_SS module

                   //R1 --> CTRL

                   MOV          R1, ADC_TSC_REGISTERS_BASE + CTRL_OFFSET

                   MOV          R2, 0x00000003

                   SBBO  R2, R1, 0, 4      

 

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

// The execution gets stuck in this "RETURN" loop, while polling the FIFO0THRESHOLD

// event. It seems like an infinite loop, an event that never happens

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

                  

RETURN:            //Load R1 with the contents of IRQSTATUS (R3 -->   IRQSTATUS)

                   LBBO  R1, R3, 0, 4

                   //Check bit 2 = FIFO0THRESHOLD event

                   QBBC  RETURN, R1.t2

                  

                   //Load R1 with the sampled value (R4 --> FIFO0DATA)

                   LBBO  R1, R4, 0, 4

                  

                   // Configure the block index register for PRU0 by setting c24_blk_index[7:0] and

                   // c25_blk_index[7:0] field to 0x00 and 0x00, respectively.  This will make C24 point

                   // to 0x00000000 (PRU0 DRAM) and C25 point to 0x00002000 (PRU1 DRAM).

                   MOV          R2, 0x00000000

                   MOV          R3, CTBIR_0

                   ST32  R2, R3

 

                   //Store sampled value

                   SBCO  R1, CONST_PRU_DRAM, 0, 4

                  

                   MOV   R31.b0, PRU0_ARM_INTERRUPT + 16

                  

                  

                   HALT