The connection between Teranet and PCIe on K2H

The payload size of PCIe module means the real payload data (excludes overhead) in each PCIe packet. The real physical SerDes throughput of PCIe will be 5Gbps(Gen2) *2 lanes = 10Gbps.

The point-to-point throughput for the TeraNet bus will be Frequency * Buswidth = CPU/3 * 128bit = 1.0GHz/3*128b = 42.67Gbps (e.g. CPU=1.0GHz). 

So for each PCIe packet, yes, the payload will be divided into multiple transaction cycles (say 256Byte/128bit = 16 cycles) inside of TeraNet to transmit to memory endpoint, but the throughput of TeraNet is big enough to maintain PCIe throughput.

Hello Steven,

I was a little confused about bit and byte. But I understand your kind reply. So, I'd like to know one more thing. What size is PCIe burst size which is like EDMA3 default burst size (DBS)?

Regards,
Kazu

Kazu,

If I understand it correctly, you would like to know about the payload size limitation of each PCIe packet, since I am not sure if burst size is applied to PCIe module.

The maximum C66x PCIe payload size is mentioned in PCIe user guide as you noticed (128B for Outbound and 256B for Inbound). But C66x PCIe module does not have built-in DMA, the data transaction is initiated by other masters (such as CPU/EDMA). And the payload size of each PCIe packet will also depend on master. If EDMA3 is being used to generate the PCIe traffic, the PCIe payload size will be the DBS of EDMA3 transfer queue (such as 64byte or 128byte). If CPU is being used, the payload size is typically 4byte (32bit). 

Hello Steven

Thank you for your reply and I'm sorry for the late reply.

It's my understanding, CPU or EDMA needs to initiate data transfer when Keystone reads and writes to remote PCIe device. But PCIESS can initiate reads/writes to memory on behalf of a remote PCI Express device. Because I suppose a max burst size which is initiated from remote PCIE device is 256 byte. What do you think?

PCIe-UG (SPRUGS6D) : 2.9 DMA Support

Regards,
Kazu