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Some questions about desktop linux sdk?

David George
Intellectual 495 points

Hi,all:


Recently,I look into desktop linux sdk.But there are some questions that I cannot understand.

1.

How PC x86 access the DDR which belongs to DSPC8681E or C6678EVM board?Who can

tell the basic theory ? I guess that PC x86 access DDR memory via PCIE interface.But I am not

sure how to achieve that ?

2.

As I know,PCIE communication between DSP and PC x86 need two side.one is RC side,the

other is EP side.it means that you must call RC driver on X86 side and call EP driver on DSP

side.But in the desktop linux sdk,I only see the x86 side has PCIE driver ,But on DSP side,I cannot

find such PCIE driver.So,Why DSP don't need such PCIE driver ? Doesn't DSP need config PCIE

register ?

3.

Can I understand the data flow like below when PC host read/write data from/to DSP?

I think there are two steps when PC read/write data from/to DSP.

first step: 

called outbound address translation .pc x86 translate internal address  to outbound address

and then translate outbound address to pcie address.

second step:

called inbound address translation .DSP receive data from pcie address ,then translate

pcie address to inbound address then translate inbound address to internal address.

Thanks,Please experts answer my question one by one directly.

  • 0
    TI__Genius 12065 points

    David,

    1. PCIe link is one way for the host PC to access EVM DDR. There are PCIe boot examples document and code as follows to demonstrate the communication between Linux host and C66x DSP via PCIe link: 

    C:\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie\docs\README.pdf

    C:\ti\mcsdk_2_01_02_06\tools\boot_loader\examples\pcie

    2. There will be driver running on PC host and also on C66x DSP. The PCIe module on DSP could be initialized by bootROM code in PCIe boot mode, and it could also be initialized by other PCIe application code loaded on DSP.

    Please refer to the example above as well for the PCIe setup on both PC host and DSP.

    3. Both of the Outbound and Inbound address translation are optional in C66x PCIe module (for PC host, please refer to the user guide of the PCIe module on the host). If the address translation feature is disabled, it means the PCIe address from C66x DSP will the same as PCIe data space address (from 0x60000000). And the PCIe address coming into C66x DSP will be whatever on the PCIe link and forward to C66x.

    It gives us more flexibility after enabling the address translation. Basically for C66x PCIe Outbound translation, the PCIe data space address will be translated to the outbound address programmed in outbound translation registers and become the PCIe packet address transmitted over the PCIe link. So on the other end, the PC host will only need to accept the PCIe addresses after outbound translation.

    For C66x PCIe Inbound translation, the PCIe packets addresses on the link will be translated to inbound addresses programmed in inbound translation registers. So the PCIe address after inbound translation could be C66x internal memory address (such as L2SRAM/DDR/MSMC SRAM). So both PC host and C66x DSP does not need to care which PCIe addresses being used over the link, but C66x could translate the incoming packets addresses to the desired destination address within C66x DSP.

    There are more detailed Outbound/Inbound translation examples mentioned in C66x PCIe user guide and PCIe use case application note. 

    Hope they could help as well.

  • 0 in reply to Steven Ji
    Expert 1690 points

    Hi,Steven:

    Thank you for your detailed reply.

    But,I think PCIE is more complex than Hyperlink. I have successed to transfer data between

    DSPs via hyperlink.I think transfer between DSPs via hyperlink is very simple and easy to understand.

    Fox example,If DSPA want to move data to DSPB.You just need to do only one thing which is mapping 

    DSPB's memory you want to access to DSPA's hyperlink data space (from 0x4000 0000).Then you can

    access DSPB's memory like visiting his memory.

         But as to PCIE,I meet so many terms like inbound ,outbound that make things so complex.Why we need

    inbound and outbound?  Why PCIE don't like Hyperlink which I say above If DSPA access DSPB's memory you

    only need to map DSPB's memory to DSPA's PCIE data space address (from 0x6000 0000) .Any all,I think PCIE

    address translation is more complex than hyperlink .I have to spend some time to look into that.

        Do you agree with me about the difference between PCIE and hyperlink data transfer?

  • 0 in reply to steve zhang
    TI__Genius 12065 points

    Steve,

    PCIe is the standard protocol for high-speed serial computer expansion bus design, which is developed and maintained by lots of companies and groups. It is different from HyperLink, which is the protocol developed by TI for high-speed communication between KeyStone devices. 

    I agree that the learning curve of PCIe protocol might be a littler longer than HyperLink. PCIe could be suitable if we have multiple PCIe Endpoint devices to be connected by switch and controlled by PC host or PCIe Root Complex device. It can also be used for point-to-point communication. But for the point-to-point communication between KeyStone devices, free feel to use HyperLink, which could provide high speed, low pin count and might be easier for the usage.

  • 0 in reply to Steven Ji
    Expert 1690 points

    Hi,Steven:

    I know the point what you say above telling the difference between pcie and hyperlink.But you don't

    reply my question directly.

          My question is how DSPA access DSPB's memory (msmc/l2sram/ddr) via pcie.How dspA read/write

    dspB's memory via pcie interface? Would you reply this question directly? I have learned some examples

    which tell that ,But I still have problem.Would you explain the basic principle about how dspA access dspB's

    memory via pcie?

          For clarifying more,Taking a example like below:

    Addr_A  : 0x8000 0000  located in dspA DDR.

    Addr_B  : 0x8000 0000  located in dspB DDR

    How write the data from dspA's Addr_A to dspB's Addr_B?

    How read data from dspB's Addr_B to dspA's Addr_A?

  • 0 in reply to steve zhang
    TI__Genius 12065 points

    Steve,

    Sorry that I missed your point before. As you may already understand from the other examples in PCIe user guide and PCIe use case app note, the Outbound and Inbound address translation in PCIe is optional abut will be necessary in many cases.

    In your example, you can enable Outbound translation in DSP_A and Inbound translation in DSP_B for the PCIe transfer initiated on DSP_A side, such as:

    DSP_A:

    For Outbound, OB_XLT_EN=1 in CMD_STATUS register (enable OB translation), OB_SIZE=0 (1MB window size by default), OB_OFFSET_INDEX0 = 0xA0000001 (offset=0xA0000000,match BAR1 in DSP_B, OB region 0 is enabled), OB_OFFSET0_HI=0 (no higher 32bit needed).

    DSP_B: 

    For Inbound, IB_XLT_EN=1 in CMD_STATUS register (enable IB translation), BAR1 = 0xA00000008 (match OB_OFFSET in DSP_A), IB_BAR0=1 (choose BAR1 in DSP_B), IB_START0_LO=0x80000000 (match destination in DSP_B), IB_START0_HI=0 (no higher 32bit needed).

    Please note the OB_OFFSET address is the PCIe address over PCIe link, it is not related to SoC internal address (0xA0000000 is the 32-bit address chosen randomly, not related to any DDR3 addresses in DSP_A or DSP_B).

    After that, the first 1MB of PCIe data space address (0x60000000~0x600FFFFF) in DSP_A will be translated to 0xA0000000~0xA00FFFFF and will be accepted by DSP_B. And the incoming addresses will be translated based on IB registers and remapped to 0x80000000~0x800FFFFF in DSP_B.

    For data write from DSP_A's Addr_A to DSP_B's Addr_B, src=0x80000000, dst=0x60000000 for CPU/EDMA initiated PCIe transfer in DSP_A.

    For data read from DSP_B's Addr_B to DSP_A's Addr_A, src=0x60000000, dst=0x80000000 for CPU/EDMA initiated PCIe transfer in DSP_A.

    It is similar for the PCIe transfer initiated in DSP_B if you enable Outbound translation in DSP_B and Inbound translation in DSP_A.

    Again, there are some similar examples and details in PCIe user guide, PCIe use case app note and the PCIe LLD example in MCSDK/PDK package for data transfer/address translation usage. Hope they could help.