C66x SRIO BER testing incoming direction

Hello, I'm currently testing the SRIO connection between C66x DSP and an FPGA. Starting point was the SRIO_LoopbackTestProject from C6657 PDK 1.1.2.6. The code was modified to normal mode (no loop-back) and single-port, two-lane operation at 5Gbps. The tests were modified to start with a slightly modified DIO test that writes to a certain location on the remote side, then reads back and finally compares the data. The test is currently not stable, so I tried to analyze the links on lower level. I run the test through all initialization code and hold execution right before the DIO test. Then I patch the SerDes Transmit Channel Configuration Registers (SERDES_CFGTXn_CNTL) to 7-bit or 31-bit PRBS test pattern. On the FPGA side I see error free reception at 5Gbps on both lanes I use. Patching the SerDes Receive Channel Configuration Registers (SERDES_CFGRXn_CNTL) to 7-bit or 31-bit PRBS test pattern causes RX_TESTFAILx in the SerDes Macro Status Register (SRIO_SERDES_STS) to get unstable, thus changing the value frequently after refreshing the register display. Changing the transmit pattern on the FPGA side causes RX_TESTFAIL to be permanently set, so the PRBS check seems to be done actually. As the outgoing PRBS test works, I suppose that there is something disturbing the incoming PRBS tests. Is there anyone who has successfully tested incoming PRBS patterns? Best regards Guenter