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UART RX DMA in DM814x

Mughees Chohan
Intellectual 530 points
Other Parts Discussed in Thread: SYSBIOS

Hi All,

I have implemented eDMA support in RX path for UART DM814x(Cortex-A8) processor for a Real Time Operating System. My driver works perfectly if Cache is disabled but I get problems when cache is enabled. In case of cache enabled, my return buffer for rx is only partially filled with receive data (first few bytes remain zero and last few bytes contain valid data). I have tried flushing and invalidating cache before and after transfer as well, but no success. Without cache everything works fine. Is there any problem with eDMA, UART and cache or maybe I am missing something? I see that in starterware for AM335x(which is very much similar to DM814x) there is an example of UART using edma. In the cache version of this example RX DMA is NOT implemented while in the non-cache version it is. Can anyone please comment on this? Thank You.

Regards,

Mughees Ahmed Chohan

  • 0
    TI__Guru**** 170625 points

    Mughees,

    Mughees Chohan said:
    I have implemented eDMA support in RX path for UART DM814x(Cortex-A8) processor for a Real Time Operating System.

    Is this the TI RTOS (http://www.ti.com/tool/sysbios) or your custom RTOS?

    Mughees Chohan said:
    My driver works perfectly if Cache is disabled but I get problems when cache is enabled.

    Do you refer to the Cortex-A8 cache or DSP cache?

    From what I have found, the problem is not UART vs cache, but EDMA vs cache. Please see the below e2e threads:

    http://e2e.ti.com/support/embedded/tirtos/f/355/t/199723.aspx

    http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/217407.aspx

    http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/t/219010.aspx

    http://e2e.ti.com/support/embedded/starterware/f/790/t/301593.aspx

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 530 points

    Hi Pavel,

    Thanks for your prompt response. I am working with our custom RTOS using Cortex-A8 cache. I'll look at these threads also now. Thanks.

    Regards,

    Mughees

  • 0 in reply to Pavel Botev
    Intellectual 530 points

    Hi Pavel,

    I looked at some of the threads. Looks like an alignment issue. Aligning my buffer to 64 bytes solved the problem. Now it works with caches. Hmm, so I will need an aligned buffer always. But I want the user to be able to give address of even a locally declared array as rx buffer(which could be aligned to anything). I also want to avoid any intermediate copying from the buffer. Any suggestions? Guess I'll have to compromise on that. Anyways, thanks a lot.

    Regards,

    Mughees