Hi, All
gpmc + CS1 are used as norflash type interface with follwing timing settings:
bank-width = <2>; /* 16-bit data width */
gpmc,mux-add-data = <2>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
With executing readw(base) or writew(value, base), the timing can be verified with oscilloscope. As my understanding, readl is equal to readw(base) + readw(base+2), and writel(value_dword, base) is equal to writew(value_low16bit, base) + writew(value_high16bit, base+2). When executing readl(...) or writel(..), do have two bus cycles but with the same address, no address increment at all. Are there any setting I missed? It's appreciated for any comments, thanks!
BR
Cheng Shi
