Hi,
Running some power-consumption lab's here with an AM3352 during cold-boot and saw that we get ~250mW combined on MPU+CORE+DDR before anything has started (by forcing PORZ / NRESPWRON to be low).
By including all LDO outputs of the TPS6590, just feeding the VDDS* buses of the CPU I get ~500mW (still in PORZ). To me this sounds like a VERY high number, let me know if this is expected behaviour.
I haven't calculated what to expect with all system buses and ball-reset states (PU's/PD's) summarised. What is strange though is if I measure incoming power "VBAT" @ ~4V via a current probe, average is ~120mA, but in reality it's more like 7-800mA short spikes at roughly 32kHz which is highly unwanted. Any clues here? I can almost guarantee :-) nothing else on the board is live that could have this bumpy current draw. Could it be the PMIC, RTC that is unhappy for some reason?
I wish to this could be much lower as we might have very limited current during boot and would of course be nice to get rid of the spikes. Note: If I boot into MLO (via NAND) = pinmux and other peripherals are setup, then just stop in a while loop, I still see these same spikes.
TPS65... Output |
CPU in reset |
Reset released (MLO -> uboot) |
Voltage |
VDD_MPU |
108mA |
152mA |
1,10V |
VDD_CORE |
93mA |
161mA |
1,10V |
VDDS_DDR |
25mA |
110mA |
1,48V |
Thanks David