TMDSEVM6678L and the TMDSEVM6678LE via SRIO using the “CI2EVMBOC”

Lawrence Wong

I have a customer reporting:

I am attempting to connect a TMDSEVM6678L and the TMDSEVM6678LE via SRIO using the “CI2EVMBOC” breakout card. I am attempting to use the SRIO_TputBenchmarkingTestProject that can be found within the PDK. The project comes ready to use for Loopback mode, but has a Readme.txt explaining how to allow for normal SRIO use. I followed the simple instructions in the Readme and also tried switching other flags I saw called IS_BOARD_TO_BOARD" and "IS_OVER_EXTERNAL_SRIO_SWITCH".

The only
documentation I have for the BoC is:

http://processors.wiki.ti.com/images/f/fd/LC_DUAL_EVM_BoC_r0p4.pdf

which contains what looks like a factory setting that I attempted to use. There also appears to be a default factory setting printed on the board that I attempted as well.

Currently every time I run the programs within the debug printouts I see "Debug: SRIO port 0 is NOT operational." and the programs appear to hang.

Any ideas?

over 11 years ago

0 Clinton Rodgers over 11 years ago

TI__Genius 13235 points

Hi Lawrence,

There is more thorough documentation on that example in the PDK. It is a Word document titled, SRIO_Benchmarking_Example_Code_Guide, found in the following directory.

<install dir>pdk_C6678_x_x_x_x\packages\ti\drv\srio\test\tput_benchmarking\docs

Let us know if you have any additional questions.

Thanks,

Clinton

0 Lawrence Wong over 11 years ago in reply to Clinton Rodgers

TI__Genius 15770 points

Clinton,

Response from the customer:

I have followed this document (assuming I needed to follow sections 5.3, 9.4, and 10.2) and still have the same results.

The only thing that caught my eye in this document was from section 10.2: " It will take approximately 60 minutes for all tests to complete."

Could this mean that the tests are in fact running and simply taking a long time to complete? Does the "ports NOT operational" statment not effect the program?

Regards,

Lawrence

0 Clinton Rodgers over 11 years ago in reply to Lawrence Wong

TI__Genius 13235 points

Hi Lawrence,

Do they get an "SRIO port x is operational" from either EVM? They should see a console output similar to what's presented in section 12 of the documentation if the tests are running. Could they provide the full console output for us to take a look at?

My recommendation is the following:

Make sure the EVMs are in 'emulation mode' (see EVM TRM for details)
Import a clean copy of the Tput project into CCS
Modify the benchmarking.h file based on the instructions in the Word document (not the README.txt)
Build and run the consumer and producer binaries based on the Word document as well.

I have tested the above instructions on 2 C6678LE EVMs connected over the BoC.

Thanks,

Clinton

0 Lawrence Wong over 11 years ago in reply to Clinton Rodgers

TI__Genius 15770 points

Clinton,

Response from customer:

No, I did not get an "SRIO port x is operational" from either EVM.

Console Output:

[C66xx_0] ********************************

[C66xx_0] *********** CONSUMER ***********

[C66xx_0] ********************************

[C66xx_0] WARNING: Please ensure that the CONSUMER is executing before running the PRODUCER!!

[C66xx_0] Debug: Waiting for module reset...

[C66xx_0] Debug: Waiting for module local reset...

[C66xx_0] Debug: Waiting for SRIO ports to be operational...

[C66xx_0] Debug: SRIO port 0 is NOT operational.

[C66xx_0] Debug: Lanes status shows lanes formed as one 4x port

[C66xx_0] Debug: AppConfig Tx Queue: 0x2a0 Flow Id: 0

[C66xx_0] Debug: SRIO Driver Instance 0x@00861bc0 has been created

[C66xx_0] Debug: Running test in polled mode.

[C66xx_0] Debug: SRIO Driver handle 0x861bc0.

[C66xx_0]

For the recommendation steps:

1.) I have not seen "emulation mode" discussed in my version of the TRM. Is there a more up to date version that does? I know I currently have them in "no boot" mode using the DIP switches.

2.) I have done this.

3.) I have done this.

4.) I have done this.

0 Clinton Rodgers over 11 years ago in reply to Lawrence Wong

TI__Genius 13235 points

Hi Lawrence,

Can they provide the console output for the producer side too? I would also like to confirm the following:

They are starting the consumer side before the producer side
The consumer code is running on core 0 of one EVM and
The producer code is running on core 1 of the other EVM (with core 0 having been connected to run the initialization gel file)

For their comment about (1) of my previous post, having the EVMs configured for 'no boot' is good. If you look at pg. 43 of the TRM, it lists boot device as 'EMIF16 and Emulation Boot' for this configuration.

EVM6678L/LE TRM from Advantech website (rev3.0):

http://wfcache.advantech.com/support/DSPM-8301E_EVM%20(6678)-3.0/TMDSEVM6678L_Technical_Reference_Manual_2V01_0320.pdf

EVM6678L/LE support and download landing page (rev3.0):

http://www.advantech.com/Support/TI-EVM/6678le_download3.aspx

Thanks,

Clinton

0 Lawrence Wong over 11 years ago in reply to Clinton Rodgers

TI__Genius 15770 points

Clinton,

Response:

Producer output:
[C66xx_1] ********************************
[C66xx_1] *********** PRODUCER ***********
[C66xx_1] ********************************
[C66xx_1] WARNING: Please ensure that the CONSUMER is executing before running the PRODUCER!!
[C66xx_1] Debug: Waiting for module reset...
[C66xx_1] Debug: Waiting for module local reset...
[C66xx_1] Debug: Waiting for SRIO ports to be operational...
[C66xx_1] Debug: SRIO port 0 is NOT operational.
[C66xx_1] Debug: Lanes status shows lanes formed as one 4x port
[C66xx_1] Debug: AppConfig Tx Queue: 0x2a0 Flow Id: 0
[C66xx_1] Debug: SRIO Driver Instance 0x@00861ad0 has been created
[C66xx_1] Debug: Running test in polled mode.
[C66xx_1] Debug: SRIO Driver handle 0x861ad0.
[C66xx_1]
[C66xx_1]
[C66xx_1] Latency: (Type-11, 5.000GBaud, 4X, tab delimited)

2.) Yes
3.) Yes

I have also tried to run the Global_Default_Setup script before using each board as well. Using it seemed to fix clock issues I've seen on the boards (slowing down by a factor of 10).

0 Clinton Rodgers over 11 years ago in reply to Lawrence Wong

TI__Genius 13235 points

Hi Lawrence,

The 'SRIO port 0 NOT operational' is related to not getting 'port_ok'. You can suggest they adjust their VMIN setting, which is discussed in the forum post below.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/196080.aspx

Could you also find out the following?

How are they connecting to the EVMs?
What other example code have they run on the EVMs?
Have they successfully run any board-to-board code?

Thanks,

Clinton

0 Lawrence Wong over 11 years ago in reply to Clinton Rodgers

TI__Genius 15770 points

Clinton,

Customer Response:

This forum post does seem like it may help. Where should I insert the code discussed in the example within the SRIO_TputBenchmarking project? Does it have to be done at a certain point in the code?

1.) I am connecting them using the Break out Card (BoC).

2/3.) Aside from successfully running the SRIO loopback examples, I have also ran the PCIe example successfully between the boards via the BoC.

0 Lawrence Wong over 11 years ago in reply to Lawrence Wong

TI__Genius 15770 points

Clinton,

Update from the customer:

I attempted to change the VMIN_EXP field in the RIO_PLM_SPn_VMIN_EXP register(s) to 15. I did this in the SRIO throughput example in the setSRIOlanes function under SRIO_laneConfig.c

There was no difference in the output, it appears to not have worked. Should I have inserted this at a later point in the code?

0 Clinton Rodgers over 11 years ago in reply to Lawrence Wong

TI__Genius 13235 points

Hi Lawrence,

I'm testing this on my setup and will post feedback once completed.

In the meantime, can you find out:

How they are connecting from the EVM to their host machine that's running CCS (i.e. what emulator(s) are they using)?
Are they running 2 instances of CCS on the same machine connected to each EVM, as mentioned in the Tput example documentation? If not, what's their setup?
- Note that this is not the only way to run the example

Thanks,

Clinton

0 Lawrence Wong over 11 years ago in reply to Clinton Rodgers

TI__Genius 15770 points

Clinton,

Response from Customer:

1.) At the moment, I have one EVM with a mezzanine card using the Blackhawk XDS560v2 and an EVM with no mezzanine card using TI XDS100v1

2.) I did not have success with using a single instance of CCS so I have been using two instance of CCS, each running on a different computer. This setup was convenient if 2 people wanted to each use a single board at the same time. Let me know if this is an issue.

0 Clinton Rodgers over 11 years ago in reply to Lawrence Wong

TI__Genius 13235 points

Hi Lawrence,

I modified the Tput example to incorporate the VMIN setting adjustment. I did this within the 'srio_device_tput.c' file in the SrioDevice_init() function (starts on line 164 of this file). Specifically, I made the following highlighted changes. Note that I deleted a portion of the the SrioDevice_init() function to save space in the code snippet below.

int32_t SrioDevice_init (void)
{
    CSL_SrioHandle      hSrio;
    int32_t             i;
    SRIO_PE_FEATURES    peFeatures;
    SRIO_OP_CAR         opCar;
    Qmss_QueueHnd       queueHnd;
    uint8_t             isAllocated;
    uint32_t            gargbageQueue[] = { GARBAGE_LEN_QUEUE,  GARBAGE_TOUT_QUEUE,
                                            GARBAGE_RETRY_QUEUE,GARBAGE_TRANS_ERR_QUEUE,
                                            GARBAGE_PROG_QUEUE, GARBAGE_SSIZE_QUEUE };
    uint32_t            srioIDMask = (testControl.srio_isDeviceID16Bit ? 0xFFFF : 0xFF);
    uint32_t            srio_primary_ID = srio_device_ID1;
    uint32_t            srio_secondary_ID = srio_device_ID2;

    //For VMIN settings
    SRIO_PLM_VMIN_EXPONENT vminExponentConfig;

    /* CODE DELETED HERE FOR BREVITY, do not delete in your srio_device file */

    /* Configure the component tag CSR */
    CSL_SRIO_SetCompTagCSR (hSrio, 0x00000000);

    /* Configure the PLM for all the ports. */
    for (i = 0; i < 4; i++)
    {
        /* Set the PLM Port Silence Timer. */
        CSL_SRIO_SetPLMPortSilenceTimer (hSrio, i, 0x2);

        /* TODO: We need to ensure that the Port 0 is configured to support both
         * the 2x and 4x modes. The Port Width field is read only. So here we simply
         * ensure that the Input and Output ports are enabled. */
        CSL_SRIO_EnableInputPort (hSrio, i);
        CSL_SRIO_EnableOutputPort (hSrio, i);

        /* Set the PLM Port Discovery Timer. */
        CSL_SRIO_SetPLMPortDiscoveryTimer (hSrio, i, 0x2);

        /* Reset the Port Write Reception capture. */
        CSL_SRIO_SetPortWriteReceptionCapture (hSrio, i, 0x0);

        // Set VMIN to 15 as recommended
        CSL_SRIO_GetPLMPortVMinExponentConfig(hSrio, i, &vminExponentConfig);
        vminExponentConfig.vminExp = 15;
        CSL_SRIO_SetPLMPortVMinExponentConfig(hSrio, i, &vminExponentConfig);
    }

Once you have the code running on the EVMs, you can use the CCS Memory Browser in the debug view to look at the PLM Port(n) Vmin Exponent Registers. The address offset for these registers is given in the SRIO UG and the SRIO configuration registers are located at the starting address listed in the memory map of the datasheet for a given device.

For C6678, the SRIO configuration registers at located starting at logical address 0x02900000. The offset for the VMIN registers are 0x1B0BC, 0x1B13C, 0x1B1BC, 0x1B23C. So the addresses to look at are:

0x0291B0bC

0x0291B13C

0x0291B1BC

0x0291B23C

If the adjustments have been made properly, you should see an 0xF located in bits 28-24 of those registers.

Let us know if they can see the adjustments reflected in these registers.

Thanks,

Clinton

0 Lawrence Wong over 11 years ago in reply to Clinton Rodgers

TI__Genius 15770 points

Clinton,

Response from customer:

I have made the changes as instructed. All of the memory addresses have the same value of 0x0F030300. The Vmin_exp portion of these values is indeed the 28-24 bits which are "01111" or 15. So I believe the changes are in effect. However the program is still not connecting and stating "SRIO port 0 is NOT operational".

What next?

0 Clinton Rodgers over 11 years ago in reply to Lawrence Wong

TI__Genius 13235 points

Hi Lawrence,

Can you pass along the following question and debug steps to the customer?

What versions of the EVMs and BoC are they using?

Can they perform the following steps so we can narrow down where their error(s) may be:

Clean and rebuild the consumer and producer outfiles using the 'Full symbolic debug' option. Right click on the project and select 'Properties' >Build>C6000 Compiler>Debug Options:
Place a breakpoint after the SRIO initialization, but before transfers are made. While testing, I placed the breakpoint at the end on main() in benchmarking.c (around line 999, although it might be slightly different in their code):
Follow the same procedure to load and start the code on each core
For each device, load the SRIO debug gel file, which can be located at the following link: Keystone SRIO Debug Gel Script
Start at step 1 in the documentation included with the gel file and provide the results.
- Note that there is currently a bug in the gel file that will display a problem with the 4x port configuration, which is the default for the Tput example. There is no actual issue with the port width field

Once we have this info, we'll take a look and provide feedback for potential issues.

Thanks,

Clinton

0 Lawrence Wong over 11 years ago in reply to Clinton Rodgers

TI__Genius 15770 points

Clinton,

From the customer:

I have ran the scripts descriped in the documentation (in sections 1, 2, 3, and 4). I have attached the output. I halted the code just after the Srio_init function (line 870 in benchmarking.c).
I am not 100% sure what this should normally look like, but there seems to be a few items that are not configured. I noticed that there is no data rate enabled and PLM is not configured.
Where do we go from here?

Boards: Rev. 3A

C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: ********************************** SRIO LOGICAL/TRANS LAYER ERROR SCAN RESULTS ************************

C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: No Logical/Transport Errors are detected

C66xx_0: GEL Output: PATH_MODE => MODE4( 4x )

C66xx_0: GEL Output: PATH_CONFIG => 4 Lanes, a maximum of 4 ports

C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output:

********************************** SRIO PORT0 ERROR SCAN RESULTS *************************************

C66xx_0: GEL Output:

*******************************************************************************************************

C66xx_0: GEL Output: Problem(PORT_UNINITIALIZED): Port0 is not Intialized.

C66xx_0: GEL Output: Reason & Solution: The immediate SRIO peer connected to this DSP might be in Reset or its port is not configured

C66xx_0: GEL Output: Problem(PORT_WIDTH): Port0 widht **DOES NOT MATCH** with PLM path configurations

C66xx_0: GEL Output: Reason & Solution: Check PLM path configuartion settings. The current PLM path settings might not be legal

C66xx_0: GEL Output: ********************************** Peripheral Settings Control Register (PER_SET_CNTL) ******************************************************

C66xx_0: GEL Output: SERDES0_PRBS_OVR[0] ---> ##Normal## (doesnt disable physical layer ENTX0 and ENRX0 control)

C66xx_0: GEL Output: SERDES1_PRBS_OVR[1] ---> ##Normal## (doesnt disable physical layer ENTX0 and ENRX0 control)

C66xx_0: GEL Output: SERDES2_PRBS_OVR[2] ---> ##Normal## (doesnt disable physical layer ENTX0 and ENRX0 control)

C66xx_0: GEL Output: SERDES3_PRBS_OVR[3] ---> ##Normal## (doesnt disable physical layer ENTX0 and ENRX0 control)

C66xx_0: GEL Output: PRESCALER_SELECT[7:4] ---> Sets the internal clock frequency Min 44.7 and Max 89.5

C66xx_0: GEL Output: CBA_TRANS_PRI[11:9] ---> 4

C66xx_0: GEL Output: TX_PRI0_WM[14:12] ---> 8, 7, 6, 5, 4

C66xx_0: GEL Output: TX_PRI1_WM[14:12] ---> 8, 7, 6, 5, 4, 3

C66xx_0: GEL Output: TX_PRI2_WM[14:12] ---> 8, 7, 6, 5, 4, 3, 2

C66xx_0: GEL Output: PROMOTE_DIS[24] ---> ##NORMAL##

C66xx_0: GEL Output: LEND_SWAP_MODE[23:22] ---> Mode A

C66xx_0: GEL Output: BOOT_COMPLETE[24] ---> Write to read-only registers **DISABLED**

C66xx_0: GEL Output: LOG_TGT_ID_DIS[27] ---> All non-matching packets are ##DESTROYED##

C66xx_0: GEL Output: LEND_SWAP_MODE[29:28] ---> Mode A

C66xx_0: GEL Output: LEND_SWAP_MODE[31:30] ---> Mode A

C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: ********************************** GENERAL HW CONFIGURATION REGISTERS SNAPSHOT ******************************************************

C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: ********************************** Peripheral Settings Control Register (PER_SET_CNTL) ******************************************************

C66xx_0: GEL Output: SERDES0_PRBS_OVR[0] ---> ##Normal## (doesnt disable physical layer ENTX0 and ENRX0 control)

C66xx_0: GEL Output: SERDES1_PRBS_OVR[1] ---> ##Normal## (doesnt disable physical layer ENTX0 and ENRX0 control)

C66xx_0: GEL Output: SERDES2_PRBS_OVR[2] ---> ##Normal## (doesnt disable physical layer ENTX0 and ENRX0 control)

C66xx_0: GEL Output: SERDES3_PRBS_OVR[3] ---> ##Normal## (doesnt disable physical layer ENTX0 and ENRX0 control)

C66xx_0: GEL Output: PRESCALER_SELECT[7:4] ---> Sets the internal clock frequency Min 44.7 and Max 89.5

C66xx_0: GEL Output: CBA_TRANS_PRI[11:9] ---> 4

C66xx_0: GEL Output: TX_PRI0_WM[14:12] ---> 8, 7, 6, 5, 4

C66xx_0: GEL Output: TX_PRI1_WM[14:12] ---> 8, 7, 6, 5, 4, 3

C66xx_0: GEL Output: TX_PRI2_WM[14:12] ---> 8, 7, 6, 5, 4, 3, 2

C66xx_0: GEL Output: PROMOTE_DIS[24] ---> ##NORMAL##

C66xx_0: GEL Output: LEND_SWAP_MODE[23:22] ---> Mode A

C66xx_0: GEL Output: BOOT_COMPLETE[24] ---> Write to read-only registers **DISABLED**

C66xx_0: GEL Output: LOG_TGT_ID_DIS[27] ---> All non-matching packets are ##DESTROYED##

C66xx_0: GEL Output: LEND_SWAP_MODE[29:28] ---> Mode A

C66xx_0: GEL Output: LEND_SWAP_MODE[31:30] ---> Mode A

C66xx_0: GEL Output: ********************************** Peripheral Settings Control Register 1 (PER_SET_CNTL1) ******************************************************

C66xx_0: GEL Output: SYS_CLK_SEL => TX0 is the source

C66xx_0: GEL Output: LOOPBACK(Lane0) => ##Normal## operation

C66xx_0: GEL Output: LOOPBACK(Lane1) => ##Normal## operation

C66xx_0: GEL Output: LOOPBACK(Lane2) => ##Normal## operation

C66xx_0: GEL Output: LOOPBACK(Lane3) => ##Normal## operation

C66xx_0: GEL Output: COS_EN => Class of Service(COS) is **NOT A PART** of the segmentation context for the RXU

C66xx_0: GEL Output: ********************************** RapidIO DEVICEID Registers Configuration ******************************************************

C66xx_0: GEL Output: RIO_DEVID0.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID0.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID1.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID1.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID2.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID2.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID3.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID3.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID4.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID4.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID5.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID5.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID6.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID6.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID7.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID7.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID8.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID8.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID9.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID9.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID10.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID10.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID11.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID11.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID12.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID12.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID13.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID13.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID14.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID14.8BNODEID ---> 0x00

C66xx_0: GEL Output: RIO_DEVID15.16BNODEID ---> 0x0000

C66xx_0: GEL Output: RIO_DEVID15.8BNODEID ---> 0x00

C66xx_0: GEL Output: ********************************** RapidIO MULTI_ID Registers Configuration ******************************************************

C66xx_0: GEL Output: RIO_MULT_ID1.16BNODEID ---> 0xFFFF

C66xx_0: GEL Output: RIO_MULT_ID1.8BNODEID ---> 0xFF

C66xx_0: GEL Output: RIO_MULT_ID2.16BNODEID ---> 0xFFFF

C66xx_0: GEL Output: RIO_MULT_ID2.8BNODEID ---> 0xFF

C66xx_0: GEL Output: RIO_MULT_ID3.16BNODEID ---> 0xFFFF

C66xx_0: GEL Output: RIO_MULT_ID3.8BNODEID ---> 0xFF

C66xx_0: GEL Output: RIO_MULT_ID4.16BNODEID ---> 0xFFFF

C66xx_0: GEL Output: RIO_MULT_ID4.8BNODEID ---> 0xFF

C66xx_0: GEL Output: RIO_MULT_ID5.16BNODEID ---> 0xFFFF

C66xx_0: GEL Output: RIO_MULT_ID5.8BNODEID ---> 0xFF

C66xx_0: GEL Output: RIO_MULT_ID6.16BNODEID ---> 0xFFFF

C66xx_0: GEL Output: RIO_MULT_ID6.8BNODEID ---> 0xFF

C66xx_0: GEL Output: RIO_MULT_ID7.16BNODEID ---> 0xFFFF

C66xx_0: GEL Output: RIO_MULT_ID7.8BNODEID ---> 0xFF

C66xx_0: GEL Output: RIO_MULT_ID8.16BNODEID ---> 0xFFFF

C66xx_0: GEL Output: RIO_MULT_ID8.8BNODEID ---> 0xFF

C66xx_0: GEL Output: ********************************** Peripheral Global Enable Register (GBL_EN) ******************************************************

C66xx_0: GEL Output: EN[0] ---> 0x00000001 => The peripheral is to be ##ENABLED##

C66xx_0: GEL Output: ********************************** Block n Enable Register (BLKn_EN) ******************************************************

C66xx_0: GEL Output: Block0 enable[0] ---> 0x00000001 => 'set of memory-mapped registers (MMRs) for the SRIO peripheral' is to be ##ENABLED## with its clock running.

C66xx_0: GEL Output: Block1 enable[0] ---> 0x00000001 => Load/Store module(LSU) is to be ##ENABLED## with its clock running.

C66xx_0: GEL Output: Block2 enable[0] ---> 0x00000001 => memory access unit (MAU) is to be ##ENABLED## with its clock running.

C66xx_0: GEL Output: Block3 enable[0] ---> 0x00000001 => message transmit unit (TXU) is to be ##ENABLED## with its clock running.

C66xx_0: GEL Output: Block4 enable[0] ---> 0x00000001 => message receive unit (RXU) is to be ##ENABLED## with its clock running.

C66xx_0: GEL Output: Block5 enable[0] ---> 0x00000001 => SRIO port 0 is to be ##ENABLED## with its clock running.

C66xx_0: GEL Output: Block6 enable[0] ---> 0x00000001 => SRIO port 1 is to be ##ENABLED## with its clock running.

C66xx_0: GEL Output: Block7 enable[0] ---> 0x00000001 => SRIO port 2 is to be ##ENABLED## with its clock running.

C66xx_0: GEL Output: Block8 enable[0] ---> 0x00000001 => SRIO port 3 is to be ##ENABLED## with its clock running.

C66xx_0: GEL Output: Block9 enable[0] ---> 0x00000001 => Block9(TODO:add block descrip) is to be ##ENABLED## with its clock running.

C66xx_0: GEL Output: ********************************** Peripheral Identification Register (PID) ******************************************************

C66xx_0: GEL Output: MINOR[5:0] (Minor revision ID) ---> 0x00000001

C66xx_0: GEL Output: CUSTOM[7:6] (Custom revision ID) ---> 0x00000000

C66xx_0: GEL Output: MAJOR[10:8] (Major revision ID) ---> 0x00000001

C66xx_0: GEL Output: RTL[15:11] (RTL revision ID) ---> 0x00000004

C66xx_0: GEL Output: FUNC[27:16] (Peripheral Functional class) ---> 0x000004AB

C66xx_0: GEL Output: SCHEME[31:30] (Peripheral scheme field. Fixed to 0x1) ---> 0x00000001

C66xx_0: GEL Output: ********************************** Peripheral Control Register (PCR) ******************************************************

C66xx_0: GEL Output: LOCAL_DIS[3] ---> 0x00000000 => Local RX traffic is **DISCARDED**

C66xx_0: GEL Output: PEREN[2] ---> 0x00000001 => Data flow control is ##ENABLED##

C66xx_0: GEL Output: SOFT[1] ---> 0x00000000 => Hard stop. All status registers are frozen in default state. (This mode is not supported on the SRIO peripheral.)

C66xx_0: GEL Output: FREE[0] ---> 0x00000001 => Free run. Peripheral ignores the emulation suspend signal and functions normally

C66xx_0: GEL Output: *******************SRIO PORT0 CONFIGURATION *******************

C66xx_0: GEL Output: *******************Port0 Control CSR configuration*******************

C66xx_0: GEL Output: SP0_CTL.PORT_TYPE[0] => This port is a ##SERIAL PORT##

C66xx_0: GEL Output: SP0_CTL.PORT_LOCKOUT[1] => The port is ##ENABLED## to issue any packets

C66xx_0: GEL Output: SP0_CTL.DROP_PACKET_ENABLE[2] => The output port ##CONTINUES TO## try to transmit packets that have been rejected due to transmission errors

C66xx_0: GEL Output: SP0_CTL.STOP_PORT_FLD_ENC_ENABLE[3] => Even when the Output Failed-encountered bit is set, the port ##CONTINUES TO ATTEMPT## to transmit packets

C66xx_0: GEL Output: SP0_CTL.MULTICAST_PARTICIPANT[19] => Multicast-event control symbols **CANNOT BE ACCEPTED** by this port

C66xx_0: GEL Output: SP0_CTL.ERROR_CHECK_DISABLE[20] => RapidIO transmission error checking and recovery are ##ENABLED##

C66xx_0: GEL Output: SP0_CTL.INPUT_PORT_ENABLE[21] => Port is ##ENABLED## to respond to any packet

C66xx_0: GEL Output: SP0_CTL.OUTPUT_PORT_ENABLE[22] => The port is ##ENABLED## to issue any packets

C66xx_0: GEL Output: SP0_CTL.PORT_DISABLE[23] => Port receivers/drivers are ##ENABLED##

C66xx_0: GEL Output: SP0_CTL.OVER_PWIDTH[26:24] => No override

C66xx_0: GEL Output: SP0_CTL.INIT_PWIDTH[29:27] => Single-lane port, lane 0

C66xx_0: GEL Output: SP0_CTL.PORT_WIDTH_BIT1[30] => 4x mode ##SUPPORTED##

C66xx_0: GEL Output: SP0_CTL.PORT_WIDTH_BIT0[31] => 2x mode ##SUPPORTED##

C66xx_0: GEL Output: ******************* Port0 Control2 CSR configuration *******************

C66xx_0: GEL Output: RTEC_EN => Remote transmit emphasis control is **DISABLED**

C66xx_0: GEL Output: RTEC => The port **DOES NOT** support remote transmit emphasis adjustment in the connected port

C66xx_0: GEL Output: D_SCRM_DIS => Transmit data scrambler and receive data descrambler are ##ENABLED##

C66xx_0: GEL Output: INACT_EN => Lanes assigned to the port but not used by the port have their outputs **DISABLED**

C66xx_0: GEL Output: GB_6p25_EN => 6.25 GBaud operation **DISABLED**

C66xx_0: GEL Output: GB_6p25 => 6.25 GBaud operation ##SUPPORTED##

C66xx_0: GEL Output: GB_5p0_EN => 5 GBaud operation **DISABLED**

C66xx_0: GEL Output: GB_5p0 => 5 GBaud operation ##SUPPORTED##

C66xx_0: GEL Output: GB_3p125_EN => 3.125 GBaud operation **DISABLED**

C66xx_0: GEL Output: GB_3p125 => 3.125 GBaud operation ##SUPPORTED##

C66xx_0: GEL Output: GB_2p5_EN => 2.5 GBaud operation **DISABLED**

C66xx_0: GEL Output: GB_2p5 => 2.5 GBaud operation ##SUPPORTED##

C66xx_0: GEL Output: GB_1p25_EN => 1.25 GBaud operation **DISABLED**

C66xx_0: GEL Output: GB_1p25 => 1.25 GBaud operation ##SUPPORTED##

C66xx_0: GEL Output: BAUD_DISC => Automatic baud rate discovery **NOT SUPPORTED**

C66xx_0: GEL Output: BAUD_SEL => No rate selected

C66xx_0: GEL Output: *******************Port0 Error Rate Enable CSR configuration*******************

C66xx_0: GEL Output: SP0_RATE_EN.LINK_TIMEOUT_EN[0] => **DISABLE** error rate counting of link timeout errors

C66xx_0: GEL Output: SP0_RATE_EN.UNSOLICITED_ACK_CNTL_SYM_EN[1] => **DISABLE** error rate counting of unsolicited acknowledge control symbols.

C66xx_0: GEL Output: SP0_RATE_EN.DELINEATION_ERROR_EN[2] => **DISABLE** error rate counting of delineation errors

C66xx_0: GEL Output: SP0_RATE_EN.PROTOCOL_ERROR_EN[4] => **DISABLE** error rate counting of protocol errors

C66xx_0: GEL Output: SP0_RATE_EN.NON_OUTSTANDING_ACKID_EN[5] => **DISABLE** error rate counting of link-responses received with an ackID that is not outstanding.

C66xx_0: GEL Output: SP0_RATE_EN.DSCRAM_LOS_EN[14] => **DISABLE** error rate counting of the loss of receiver de-scrambler synchronization

C66xx_0: GEL Output: SP0_RATE_EN.RCVED_PKT_OVER_276B_EN[17] => **DISABLE** error rate counting of packets that exceed the maximum allowed size

C66xx_0: GEL Output: SP0_RATE_EN.RCVED_PKT_WITH_BAD_CRC_EN[18] => **DISABLE** error rate counting of packets with a bad CRC values

C66xx_0: GEL Output: SP0_RATE_EN.PKT_UNEXPECTED_ACKID_EN[19] => **DISABLE** error rate counting of packets with unexpected/out-of-sequence ackIDs

C66xx_0: GEL Output: SP0_RATE_EN.RCVED_PKT_NOT_ACCPT_EN[20] => **DISABLE** error rate counting of received packet-not-accepted control symbols.

C66xx_0: GEL Output: SP0_RATE_EN.CNTL_SYM_UNEXPECTED_ACKID_EN[21] => **DISABLE** error rate counting of an acknowledge control symbol with an unexpected ackID

C66xx_0: GEL Output: SP0_RATE_EN.CORRUPT_CNTL_SYM_ENABLE[22] => **DISABLE** error rate counting of a corrupt control symbol

C66xx_0: GEL Output: SP0_RATE_EN.EN_IMP_SPECIFIC[31] => **DISABLE** error rate counting of implementation specific errors

C66xx_0: GEL Output: *******************Port0 Error Rate CSR configuration*******************

C66xx_0: GEL Output: SP0_ERR_RATE.ERROR_RATE_BIAS[31:24] => Reserved

C66xx_0: GEL Output: SP0_ERR_RATE.ERROR_RATE_RECOVERY[17:16] => Only count 2 errors & above

C66xx_0: GEL Output: *******************Port0 Error Rate Threshold CSR configuration*******************

C66xx_0: GEL Output: SP0_ERR_THRESH.ERROR_RATE_DEGRADED_THRESH[23:16] ---> 255

C66xx_0: GEL Output: SP0_ERR_THRESH.ERROR_RATE_FAILED_THRESH[31:24] ---> 255

C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: ********************************** COMMON PORT CONFIGURATION REGISTERS SNAPSHOT ******************************************************

C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: ********************************** Port Link Time-Out Control CSR (SP_LT_CTL) ******************************************************

C66xx_0: GEL Output: TVAL ---> 0.0 to 0.0 sec (srio_ip_clk - 312.5 MHz)

C66xx_0: GEL Output: ********************************** Port Response Time-Out Control CSR (SP_RT_CTL) ******************************************************

C66xx_0: GEL Output: TIMEOUT_VALUE[31:8] ---> 0x00000000FF => 7650.0 ns

C66xx_0: GEL Output: ********************************** Port General Control CSR (SP_GEN_CTL) ******************************************************

C66xx_0: GEL Output: DISCOVERED[29] ---> 0x00000000 => The device has not been previously discovered

C66xx_0: GEL Output: MASTER_ENABLE[30] ---> 0x00000001 => Processing element can issue requests

C66xx_0: GEL Output: HOST[31] ---> 0x00000000 => Agent or Slave device

C66xx_0: GEL Output: ********************************** Port-Write Target Device ID CSR (PW_TGT_ID) ******************************************************

C66xx_0: GEL Output: ID_LARGE[15] ---> 0x00000000 => 8-bit device ID for port-write operation

C66xx_0: GEL Output: DEVICEID[23:16] ---> 0x00000000

C66xx_0: GEL Output: DEVICEID_MSB[31:24] ---> 0x00000000

C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: ********************************** LOGICAL/TRANSPORT LAYER CONFIGURATION REGISTERS SNAPSHOT ******************************************************

C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: ********************************** Logical/Transport Layer Error Enable CSR (ERR_EN) ******************************************************

C66xx_0: GEL Output: RX_IO_SECURITY_ENABLE[6] => **DISABLE** reporting of attempt at unauthorized access to a memory location.

C66xx_0: GEL Output: RX_CPPI_SECURITY_ENABLE[7] => **DISABLE** reporting of an attempt at unauthorized access to a RX queue

C66xx_0: GEL Output: UNSUPPORTED_TRANS_ENABLE[22] => **DISABLE** reporting of an unsupported transaction error

C66xx_0: GEL Output: UNSOLICITED_RESP_ENABLE[23] => **DISABLE** reporting of an unsolicited response error

C66xx_0: GEL Output: PKT_RESP_TIMEOUT_ENABLE[24] => **DISABLE** reporting of a packet response time-out error

C66xx_0: GEL Output: MSG_REQ_TIMEOUT_ENABLE[25] => **DISABLE** reporting of a message request time-out error

C66xx_0: GEL Output: ILL_TRANS_DECODE_ENABLE[27] => **DISABLE** reporting of an illegal transaction decode error

C66xx_0: GEL Output: ERR_MSG_FORMAT_ENABLE[28] => **DISABLE** reporting of a message format error

C66xx_0: GEL Output: MSG_ERR_RESP_ENABLE[30] => **DISABLE** reporting of a message error response

C66xx_0: GEL Output: IO_ERR_RESP_ENABLE[31] => **DISABLE** reporting of an IO error response

C66xx_0: GEL Output: ********************************** Processing Element Logical Layer Control CSR (PE_LL_CTL) ******************************************************

C66xx_0: GEL Output: EXTENDED_ADDRESSING_CONTROL[8] => PE supports 34 bit addresses

C66xx_0: GEL Output: *****************************SRIO HW Global Enable Status*****************************

C66xx_0: GEL Output: Global enable status ---> 0x00000001 => The peripheral is enabled with all its clocks running

C66xx_0: GEL Output: Block0 enable status ---> 0x00000001 => 'set of memory-mapped registers (MMRs) for the SRIO peripheral' is enabled with its clock running.

C66xx_0: GEL Output: Block1 enable status ---> 0x00000001 => Load/Store module(LSU) is enabled with its clock running.

C66xx_0: GEL Output: Block2 enable status ---> 0x00000001 => memory access unit (MAU) is enabled with its clock running.

C66xx_0: GEL Output: Block3 enable status ---> 0x00000001 => message transmit unit (TXU) is enabled with its clock running.

C66xx_0: GEL Output: Block4 enable status ---> 0x00000001 => message receive unit (RXU) is enabled with its clock running.

C66xx_0: GEL Output: Block5 enable status ---> 0x00000001 => SRIO port 0 is enabled with its clock running.

C66xx_0: GEL Output: Block6 enable status ---> 0x00000001 => SRIO port 1 is enabled with its clock running.

C66xx_0: GEL Output: Block7 enable status ---> 0x00000001 => SRIO port 2 is enabled with its clock running.

C66xx_0: GEL Output: Block8 enable status ---> 0x00000001 => SRIO port 3 is enabled with its clock running.

C66xx_0: GEL Output: Block9 enable status ---> 0x00000001 => Block9 is enabled with its clock running.

C66xx_0: GEL Output: ********************************** SRIO PORT0 STATUS ******************************************************

C66xx_0: GEL Output: *******************Port0 Error and Status CSR*******************

C66xx_0: GEL Output: PORT_UNINITIALIZED => Input and output ports are **NOT INITIALIZED**

C66xx_0: GEL Output: PORT_OK => Port **NOT-OK** condition

C66xx_0: GEL Output: PORT_ERROR => The input or output port ##HAS NOT ENCOUNTERED## an unrecoverable HW error

C66xx_0: GEL Output: PORT_UNAVL => The port is ##AVAILABLE## for use

C66xx_0: GEL Output: PORT_WRITE_PND => The port ##HAS NOT ENCOUNTERED## a condition which required it to initiate a Maintenance Port-write operation

C66xx_0: GEL Output: INPUT_ERROR_STP => The input port ##IS NOT## in the 'input error-stopped' state

C66xx_0: GEL Output: INPUT_ERROR_ENC => The input port ##HAS NOT ENCOUNTERED## a transmission error

C66xx_0: GEL Output: INPUT_RETRY_STP => The input port ##IS NOT## in the 'input retry-stopped' state

C66xx_0: GEL Output: OUTPUT_ERROR_STP => The output port ##IS NOT## in the 'output error-stopped' state

C66xx_0: GEL Output: OUTPUT_ERROR_ENC => The output port ##HAS NOT ENCOUNTERED## a transmission error

C66xx_0: GEL Output: OUTPUT_RETRY_STP => The output port ##HAS NOT RECEIVED## a packet-retry control symbol and/or is not in the 'output retry-stopped' state.

C66xx_0: GEL Output: OUTPUT_RETRIED => The output port ##HAS NOT RECEIVED## a packet-retry control symbol and cannot make forward progress.

C66xx_0: GEL Output: OUTPUT_RETRY_ENC => The output port ##HAS NOT ENCOUNTERED## a retry condition

C66xx_0: GEL Output: OUTPUT_DEGRD_ENC => The output port ##HAS NOT ENCOUNTERED## a degraded condition

C66xx_0: GEL Output: OUTPUT_FLD_ENC => The output port ##HAS NOT ENCOUNTERED## a failed condition

C66xx_0: GEL Output: OUTPUT_PKT_DROP => The output port ##HAS NOT DISCARDED## a packet

C66xx_0: GEL Output: TXFC => Receiver-based flow control

C66xx_0: GEL Output: IDLE_SEQ => Idle sequence 1 is active.

C66xx_0: GEL Output: IDLE2_EN => Idle sequence 2 **DISABLED** for baud rates < 5.5 GBaud

C66xx_0: GEL Output: IDLE2 => Idle sequence 2 **NOT SUPPORTED** for baud rates < 5.5 GBaud

C66xx_0: GEL Output: *******************Port0 Error Detect CSR*******************

C66xx_0: GEL Output: LINK_TIMEOUT => The port ##DID NOT EXPERIENCE## a link timeout

C66xx_0: GEL Output: UNSOLICITED_ACK_CNTL_SYM => The port ##DID NOT RECEIVE## an unexpected acknowledge control symbol

C66xx_0: GEL Output: DELINEATION_ERROR => The port ##DID NOT DETECT## a delineation error

C66xx_0: GEL Output: PROTOCOL_ERROR => The port ##DID NOT RECEIVE## an unexpected packet or control symbol

C66xx_0: GEL Output: NON_OUTSTANDING_ACKID => The port ##DID NOT RECEIVE## a link response with a non-outstanding ackID

C66xx_0: GEL Output: DSCRAM_LOS => Receiver de-scrambler synchronization is ##NOT LOST##

C66xx_0: GEL Output: RCVD_PKT_OVER_276B => The port ##DID NOT RECEIVE## packet that exceeds the maximum allowed size.

C66xx_0: GEL Output: RCVD_PKT_WITH_BAD_CRC => The port ##DID NOT RECEIVE## a packet with a bad CRC value

C66xx_0: GEL Output: PKT_UNEXPECTED_ACKID => The port ##DID NOT RECEIVE## a packet with unexpected/out-of-sequence ackID

C66xx_0: GEL Output: RCVD_PKT_NOT_ACCPT => The port ##DID NOT RECEIVE## a packet-not-accepted acknowledge control symbol.

C66xx_0: GEL Output: CNTL_SYM_UNEXPECTED_ACKID => The port ##DID NOT RECEIVE## an acknowledge control symbol with an unexpected ackID (packet-accepted or packet-retry)

C66xx_0: GEL Output: CORRUPT_CNTL_SYM => The port ##DID NOT RECEIVE## a control symbol with a bad CRC value

C66xx_0: GEL Output: ERR_IMP_SPECIFIC => An implementation specific error ##HAS NOT BEEN## detected

C66xx_0: GEL Output: *******************Port0 Error rate CSR*******************

C66xx_0: GEL Output: ERROR_RATE_COUNTER ---> 0

C66xx_0: GEL Output: PEAK_ERROR_RATE ---> 0

C66xx_0: GEL Output: *******************Port0 Link Maintenance Response CSR data*******************

C66xx_0: GEL Output: LINK_STATUS ---> Reserved

C66xx_0: GEL Output: ACKID_STATUS ---> 0x00

C66xx_0: GEL Output: RESPONSE_VALID ---> Response ##IS NOT## valid

C66xx_0: GEL Output: *******************Port0 Local AckId Status CSR*******************

C66xx_0: GEL Output: OUTBOUND_ACKID ---> 0x00

C66xx_0: GEL Output: OUTSTANDING_ACKID ---> 0x00

C66xx_0: GEL Output: INBOUND_ACKID ---> 0x00

C66xx_0: GEL Output: *******************Port0 Attributes Error Capture CSR*******************

C66xx_0: GEL Output: CAPTURE_VALID_INFO ---> The packet/control symbol capture registers ##DO NOT CONTAIN## valid information.

C66xx_0: GEL Output: IMP_SPECIFIC ---> 0x00000000

C66xx_0: GEL Output: ERROR_TYPE ---> 0x00

C66xx_0: GEL Output: INFO_TYPE ---> Packet

C66xx_0: GEL Output: CAPTURE0 ---> 0x00000000

C66xx_0: GEL Output: CAPTURE1 ---> 0x00000000

C66xx_0: GEL Output: CAPTURE2 ---> 0x00000000

C66xx_0: GEL Output: CAPTURE3 ---> 0x00000000

C66xx_0: GEL Output: ******************* PORT0 PLM STATUS *******************

C66xx_0: GEL Output: ******************* PLM Port Power Down Control Register (PLM_SP0_PWDN_CTL) *******************

C66xx_0: GEL Output: Port0 is in ##NORMAL## mode

C66xx_0: GEL Output: ******************* PLM Port Event Status Register(PLM_SP0_Status) *******************

C66xx_0: GEL Output: TLM_INT => Port0 TLM has ##NOT DETECTED## an event, which requires interrupt notification.

C66xx_0: GEL Output: PBM_INT => Port0 PBM has ##NOT DETECTED## an event, which requires interrupt notification.

C66xx_0: GEL Output: MECS => Port0 has ##NOT RECEIVED## a Multi-cast Event Control Symbol

C66xx_0: GEL Output: TLM_PW => Port0 TLM has ##NOT DETECTED## an event, which requires Port-Write notification

C66xx_0: GEL Output: PBM_PW => Port0 PBM has ##NOT DETECTED## an event, which requires Port-Write notification

C66xx_0: GEL Output: RST_REQ => Port0 has ##NOT RECEIVED## a reset request command

C66xx_0: GEL Output: OUTPUT_DEGR => Port0 is ##NOT## in output degraded condition

C66xx_0: GEL Output: OUTPUT_FAIL => Port0 is ##NOT## in output failed condition

C66xx_0: GEL Output: PORT_ERR => Port0 has ##NOT ENCOUNTERED## a unrecoverable HW error

C66xx_0: GEL Output: DLT => Port0 has ##NOT DETECTED## that its link partner has been removed

C66xx_0: GEL Output: LINK_INIT => Port0 Link Initialization **UNSUCCESSFUL**

C66xx_0: GEL Output: MAX_DENIAL => Port0 has ##NOT EXCEEDED## the denial threshold

C66xx_0: GEL Output: ******************* PLM Port Received MECS Status Register(PLM_SP0_RCVD_MECS) *******************

C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=0

C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=1

C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=2

C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=3

C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=4

C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=5

C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=6

C66xx_0: GEL Output: Port0 ##DID NOT RECEIVE## MECS with cmd=7

C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: ********************************** LLM CONFIGURATION ******************************************************

C66xx_0: GEL Output: *******************************************************************************************************

C66xx_0: GEL Output: ******************* Port Number CSR (PORT_NUMBER) *******************

C66xx_0: GEL Output: PORT_NUM => Maintenance read operation accessed this register through Port0

C66xx_0: GEL Output: PORT_TOTAL => Total number of Ports are 4

C66xx_0: GEL Output: ******************* Port IP Prescalar for SRV_CLK Register(PRESCALAR_SRV_CLK) *******************

C66xx_0: GEL Output: PRESCALAR_SRV_CLK => 31 (srio_ip_clk of 312.5 MHz)

C66xx_0: GEL Output: SRV_CLK_PERIOD => 0.0992 us

C66xx_0: GEL Output: ******************* Register Reset Control CSR (REG_RST_CTL) *******************

C66xx_0: GEL Output: CLEAR_STICKY => Sticky bits are **CLEARED** by SELF_RST and PWDN_PORT

C66xx_0: GEL Output: ******************* Local Logical/Transport Layer Error Enable CSR (LOCAL_ERR_EN)*******************

C66xx_0: GEL Output: ILL_TYPE_EN => Unsupported Transaction error reporting ##DISABLED##

C66xx_0: GEL Output: ILL_ID_EN => Illegal transaction target error reporting ##DISABLED##

0 Clinton Rodgers over 11 years ago in reply to Lawrence Wong

TI__Genius 13235 points

Hi Lawrence,

I've attached the Tput project I'm using for reference. Included in the project directory structure is a folder called 'Binaries', which contains pre-built binaries that i've tested on my setup. I would suggest using the consumer and producer binaries with the VMIN setting adjustments incorporated.

I also noticed you mentioned that the customer is using rev 3A of the EVM. I'm using rev 3B. The differences between these board revisions should be reviewed.

I'm also using the evmc6678l.gel file and performing a 'Global Default Setup' on core 0 of each device. This gel file can be located in the following location:

<install dir>\ccsv5\ccs_base\emulation\boards\evmc6678l\gel

Here's the console output from running this default setup:

C66xx_0: GEL Output: DSP core #0
C66xx_0: GEL Output: C6678L GEL file Ver is 2.005
C66xx_0: GEL Output: Global Default Setup...
C66xx_0: GEL Output: Setup Cache...
C66xx_0: GEL Output: L1P = 32K
C66xx_0: GEL Output: L1D = 32K
C66xx_0: GEL Output: L2 = ALL SRAM
C66xx_0: GEL Output: Setup Cache... Done.
C66xx_0: GEL Output: Main PLL (PLL1) Setup ...
C66xx_0: GEL Output: PLL in Bypass ...
C66xx_0: GEL Output: PLL1 Setup for DSP @ 1000.0 MHz.
C66xx_0: GEL Output: SYSCLK2 = 333.3333 MHz, SYSCLK5 = 200.0 MHz.
C66xx_0: GEL Output: SYSCLK8 = 15.625 MHz.
C66xx_0: GEL Output: PLL1 Setup... Done.
C66xx_0: GEL Output: Power on all PSC modules and DSP domains...
C66xx_0: GEL Output: Security Accelerator disabled!
C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done.
C66xx_0: GEL Output: PA PLL (PLL3) Setup ...
C66xx_0: GEL Output: PA PLL Setup... Done.
C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ...
C66xx_0: GEL Output: DDR3 PLL Setup... Done.
C66xx_0: GEL Output: DDR begin (1333 auto)
C66xx_0: GEL Output: XMC Setup ... Done

8322.8156.Tput_tested.zip

Thanks,

Clinton

0 Lawrence Wong over 11 years ago in reply to Clinton Rodgers

TI__Genius 15770 points

Clinton,

Advantech only shows Rev 3A board. http://www.advantech.com/Support/TI-EVM/6678le_download3.aspx Where are the Rev 3B board schematic?

From the customer:

i ran the code you sent me. All versions appear to have the same output which I have included in the attached word docs. They appear to get slightly further, but the ports are still not operational and the program hangs. You mentioned differences between boards 3A and 3B, what differences could effect this? should I be using a different version of the PDK to run on a 3A board?3755.4885.consumer output.docx 6470.3858.Producer output.docx

0 Mukul Bhatnagar over 11 years ago in reply to Lawrence Wong

TI__Guru* 83855 points

Updates on this thread

It appears that the issue was root caused to

1) Difference in the boot configuration pin setup on one of the EVM in customer's setup

2) Possibly an older version of the GEL file being used by the customer

No difference due to EVM 3A vs 3B.

The latest greatest example and gel files available for download from the following page

http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/latest/index_FDS.html

GEL files part of the TI_EMU pack.

Regards

Mukul

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