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C6657-- signal length of RTCK question

TI Lady
Genius 4025 points

The above document states in numerous places that the total signal length of the RTCK etc should not be greater than 3”. We have implemented a system similar to the evaluation card where either the 60 pin header can be used or simple JTAG header via IC switches can be used to access the DSP debug. With this we are struggling to meet this 3” restriction, we currently have 4.5”. I have looked at this on the evaluation layout to see how it was achieved and it on this PCB the signal length is 9.3” and it works. Can anyone comment on this?

 1768.Emulation.pdf


thank you.

  • 0
    TI__Mastermind 42545 points

    The 3" length is intended to minimize the effects of the routing on the board to the signal integrity of the signals. A badly routed 3" could be worse than a well routed 4.5". The clock signal routing is the most important. Any glitch on the clock edge will prevent your JTAG interface from operating reliably. Although it is not a requirement in the document that you reference, I highly recommend that you buffer the clocks at a minimum. Connect the TCK to the input of two buffers and route the output of one to the device and the second to RTCK. This will help to minimize the reflections and prevent glitches on the clock edge. If you are not buffering the TCK signal, you should simulate your design to ensure that glitches are not present.

    Regards, Bill