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DM8148 both EMAC 0 & 1 as RMII mode

Other Parts Discussed in Thread: DP83848K, CDCVF2505

Hi Folks,


I am operating DM8148 both EMAC0 and EMAC1 as RMII mode.

I don't have pins available to operate in other modes.

DM8148 is having one RMII Ref clock pin ( i am using as default state - operating in output 50MHz clock out). I am sourcing this clock to Two Physical Transceiver IC's  DP83848K through buffer CDCVF2505.

I want to configure two EMAC's as two different IP's.

If i run two EMAC's parley , am i face any issues with respect to processor internal architecture(because it is having single clock)

am i able to run in Both EMAC's as RMII  mode?

I am in urgent need. Can You please somebody explain about this, how RMII will operate DM8148 internally.

Thanks You,

Regards

Swapna.B

  • Hi Swapna,

    Please go through the below links:

    http://processors.wiki.ti.com/index.php/TI81xx_PSP_Porting_Guide#CPSW_RMII_Phy

    http://processors.wiki.ti.com/index.php/TI81xx_PSP_Porting_Guide#CPSW_EMAC_1_bringup_in_uboot

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_ETHERNET_Switch_User_Guide

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/247403.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/171407.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/154601.aspx

    http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/716/t/128609.aspx

    Regards,
    Pavel

  • Hi Pavel,

    I have already gone through above links.

    As per datasheet , we can configure Both EMAC's as RMII mode.But DM8148 is having single RMII Ref clock.

    But how come single can be use, what is the mechanism here to work both EMAC as RMII mode.

    Thanks,

    Regards

    Swapna.B

  • Swapna,

    swapna bramandlapally1 said:
    As per datasheet , we can configure Both EMAC's as RMII mode.But DM8148 is having single RMII Ref clock.

    This RMII Ref clock is input to the Ethernet subsystem, which subsystem contains the two EMAC/Ethernet ports (EMAC0 and EMAC1).

    For detailed RMII Ref clock architecture, see DM814x TRM:

     - section 2.3.6 SERDES and Ethernet Clock Structure with figure 2-10

    -  section 9.1.5.1 Subsystem clocking with figure 9-2

    - section 9.1.8 3PSW Ports

    Ethernet Subsystem has 3 Ports. Port 0 is the Host port (internal to the Subsystem). Ports 1 and 2 are the
    external ports connected to G/MII, RGMII, or RMII interfaces as per the interface selected.
    Naming conventions followed in this chapter:
    • Port0 is referred to the Host Port
    • Port1 is referred to the interfaces GMII0/RGMII0/RMII0
    • Port2 is referred to the interfaces GMII1/RGMII1/RMII1

    - section 9.2.1.5.2 Dual Mac Mode

    - section 9.2.1.7.2.4 RMII Signal Connections and Descriptions

    Regards,
    Pavel