Hi,
I've read a few posts on this forum about bit swapping using DDR3/L with the AM335x. If I understand correctly it is okay to randomly swap bits in the same Byte lanes and even swap byte lanes if DQS and DQM follows the respective byte lanes. My confusion is if a DDR3 controller is JEDEC compliant for "write leveling " which would make the Prime bits fixed and not swappable?
I have seen advice on this forum and the TMDSSK3358 which does not follow the write leveling rule. Does this mean that hardware write leveling is not working?
I saw this in a Freescale Hardware Development Guide for bit swapping on the iMX6 with DDR3/L which follows the JEDEC spec.
3.5.1 Swapping data lines
The DDR3 pin swapping technique for the data bus lines within bytes makes it easier to:
• Route direct lines
• Avoid changes between layers
The rules are as follows:
• Hardware write leveling – lowest order bit within byte lane must remain on lowest order bit of lane
by JEDEC compliance (see the “Write Leveling” section in JESD79-3E)
— D0, D8, D16, D24, D32, D40, D48, and D56 are fixed
— Other data lines free to swap within byte lane
• JEDEC DDR3 memory restrictions are:
– No restrictions for complete byte lane swapping
– DQS and DQM must follow lanes
NOTE
If byte lane swapping was done, target DDR IC register read value must be
transposed according to the data line swapping.
In my design I would like to swap bits in the same byte lanes for layout reasons but I would like to ensure that hardware write leveling in still in play. Please see the snippet below:
Also, the way the DRAM controller is laid out there is no way to avoid changing layers on the Databus unless you use blind vias.
