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UART DMA for RX on DM814x

Mughees Chohan
Intellectual 530 points

Hi,

I want to implement RX support for UART on DM814xevm platform using our own custom RTOS. The UART buffer maintained is very similar to the linux's one. I am receiving characters via DMA successfully but I want to fill my buffer the very same way the omap-serial.c(which uses SDMA not eDMA on platforms other than DM814x) driver fills for linux in case of DMA. But apparently there is no way to know the status of an ongoing transfer before its completion in eDMA, because of which the approach used in the linux driver cannot be used. Since I can know that the transfer is complete in case of dma only if complete length has been received and then fill the buffer. I cannot do that here since if the data that comes is less than the programmed length in DMA I cannot copy it to my buffer because I dont know how much data has yet been received since the interrupt for dma completion does not occur in this case and the application stuck is stuck here. Can anyone suggest what should I do to overcome this? Thank You.

Regards,

Mughees

  • 0
    Intellectual 530 points

    In case of edma is it possible to know prior to transfer completion that how much of the transfer is complete at a particular moment?

  • 0
    Intellectual 530 points

    How can SACNT register in eDMA help in this regard?

  • 0 in reply to Mughees Chohan
    TI__Guru**** 170625 points

    Mughees,

    The EDMA transfer is defined in terms of three dimensions: array (A), frame (B) and block (C). You should set up your transfer for at least 1 dimension, thus setting ACNT to some value (1 to 65 535).

    Then you can monitor your transfer progress through the read-only register SACNT:

    SACNT[15:0] ACNT - A dimension count. Number of bytes to be transferred in first dimension. It is decremented after each read command appropriately. Represents the amount of data remaining to be read. It should be 0 when
    transfer request (TR) is complete.


    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 530 points

    Hi Pavel,

    I am very new to edma. I am using edma code done by some other engineer for this support. As far as I can see there is only one SACNT register. How would I know that the current value of SACNT represents the status of serial dma transfer and not of any other peripheral. There are dma transfers going for SD/MMC, i2c and spi also in my system. SACNT tells about only the current transfer. I want to implement the algorithm implemented for serial rx dma in linux driver for other platforms like omap etc.  Thank You.

    Regards,

    Mughees

  • 0 in reply to Mughees Chohan
    TI__Guru**** 170625 points

    Mughees,

    The DM814x EDMA has 1 Channel Controller (CC), 4 Transfer Controllers (TC0, TC1, TC2 and TC3), 64 independent DMA channels and 8 independent QDMA channels. 

     

    Mughees Chohan said:
    There are dma transfers going for SD/MMC, i2c and spi also in my system.

    I assume these are configured like: SD/MMC with TC0, I2C with TC1, SPI with TC2. Thus UART_RX can be mapped to TC3.

    And we have the below physical addresses for SACNT registers:

    TC0 SACNT 0x49800248
    TC1 SACNT 0x49900248
    TC2 SACNT 0x49A00240
    TC3 SACNT 0x49B00248

    Best regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 530 points

    Hi Pavel,

    You are right I can do that but my customer plans to use at least two uarts(both channels rx tx) from uart0 to uart5 along with spi, i2c, sdio and memory to memory transfers as well. In this case this approach would fail. Is there something planned for rx dma of linux driver for dm814x? I guess that customer would have to make a choice then. Thank You.

    Regards,

    Mughees

  • 0 in reply to Mughees Chohan
    TI__Guru**** 170625 points

    Mughees,

    Reading the DM814x EDMA TRM, it seems to me that you can have up to 4 DMA transfers at the same time (simultaneously).

    The EDMA3 transfer controllers are slaves to the EDMA3 channel controller that is responsible for data movement. The transfer controller issues read/write commands to the source and destination addresses that are programmed for a given transfer. The operation is transparent to user.


    The EDMA3 transfer controller has the following features:
    • Four transfer controllers (TC).
    • Up to four in-flight transfer requests (TRs).

    You can have 4 DMA transfers at the same time. Other transfers should wait the completion of the TCs.


    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 530 points

    Hmmm, looks like i'll have to dive deeper to get complete insight over this. Thanks, I'll try to catch up soon :-). Thanks a lot. 

    Best Regards,

    Mughees

  • 0 in reply to Mughees Chohan
    TI__Guru**** 170625 points

    Mughees,

    The wiki pages below might be also in help:

    http://processors.wiki.ti.com/index.php/EDMA3

    http://processors.wiki.ti.com/index.php/TI81XX_PSP_EDMA_Driver_User_Guide

    http://processors.wiki.ti.com/index.php/EDMA_sample_test_application

    Best regards,
    Pavel