OMAP5 timing dispc timing relations

Anthony Fibi

Other Parts Discussed in Thread: SYSCONFIG

Hello,

I'm currently working on driving displays in DSI video mode.

The display i'm driving has the following parameters:

xres :480        yres:800
hfp   :48          vfp   :3
hsw :32          vsw :4
hbp :80          vbp :7

Using RGB888, 2 data lanes, refresh rate of 60 and a sys_clk of 19.2MHz

I succeeded in driving this display however I had an issue of the RGB data on the DSI bus being completely black.
After quite a long time of searching i finally managed to figure out the problem.

The problem was caused by the settings for the clock dividers M4REG+1, LCD and PCD.

CLKIN2DDR =374.4MHz
LCDx_PCLK = 31.2MHz
Total divide needs to be 12
When I set these values to (M4REG+1)12, (LCD)1 and (PCD)1. The issue was present..
When i set them to (M4REG+1)3, (LCD)1 and (PCD)4 the display booted successfully.

The problem is that i do not completely understand the relation between these dividers and how they are calculated individually. The technical reference manual is unclear about these 3 except that their total needs to be correct.

Could anyone explain to me how these values are determined?

Any help would be greatly appreciated.

over 11 years ago

0 Yanko Todorov-XID over 11 years ago

TI__Mastermind 29520 points

Hello Anthony,

The CLKIN2DDR clocks are twice the DSI output clock frequency, which is equal to the data rate. The DSI
PLL factors must be calculated based on the required input and output frequencies, keeping the PLL
internal reference frequency in the appropriate range:
• REGM factor is programmed by the DSI_PLL_CONFIGURATION1[20:9] PLL_REGM bit field.
• REGN factor is programmed by the DSI_PLL_CONFIGURATION1[8:1] PLL_REGN bit field.

The M4REG and M5REG factors must be set respecting the following conditions:
- The DPLL_DSI1_x_CLK1 frequency must be a multiple of PCLK frequency (for
proper settings of the PCD and LCD factors in the DISPC).
- The DPLL_DSI1_x_CLK1 and DPLL_DSI1_x_CLK2 frequencies must be lower than
200 MHz. For more information about clock frequency ratings.

I will check your use case. Then I will give my feedback about the question.

Could you provide a log of your DSS register settings if possibly?

Best regards,

Yanko

0 Anthony Fibi over 11 years ago in reply to Yanko Todorov-XID

Prodigy 215 points

Hello Yanko,

You say that the DPLL_DSI1_x_CLK1 frequency must be a multiple of PCLK frequency.

While in case of the teisko (480*800) I'm using allows this because of a total dividend of 12.

In case of the hemmingway(1920*1080) which requires a higher data rate (428.4MHz) won't allow this.

The CLKIN2DDR is 856.8MHz and the PCLK needs to be 142.8MHz.

Total dividend is 6, because of the maximum frequency of DPLL_DSI1_x_CLK1 is 200MHz the M4REG has to be at least 5 since the dividing values have to be integers the only way to get the total dividend required is to set the values to M4REG = 6, LCD = 1 and PCD = 1.

This also means that in this case DPLL_DSI1_x_CLK1 cannot be a multiple of PCLK.

Following are the settings of the working teisko video module
Timing settings:

DDR = 187.2MHz
REGN+1 = 16
REGM = 156
M4REG+1 = 3
M5REG+1 = 3
LCD = 1
PCD = 4

REG settings:

d/omapdss/dss
DSS_REVISION                        00000061
DSS_SYSCONFIG                       00000000
DSS_SYSSTATUS                       00000001
DSS_CONTROL                         00000083

d/omapdss/dispc
DISPC_REVISION                                     00000051
DISPC_SYSCONFIG                                    00001009
DISPC_SYSSTATUS                                    00000001
DISPC_IRQSTATUS                                    000000a2
DISPC_IRQENABLE                                    0012d640
DISPC_CONTROL                                      00000309
DISPC_CONFIG                                       00020004
DISPC_CAPABLE                                      00000000
DISPC_LINE_STATUS                                  00000000
DISPC_LINE_NUMBER                                  00000000
DISPC_GLOBAL_ALPHA                                 ffffffff
DISPC_CONTROL2                                     00000000
DISPC_CONFIG2                                      00000000
DISPC_DEFAULT_COLOR(LCD)                           00000000
DISPC_TRANS_COLOR(LCD)                             00000000
DISPC_SIZE_MGR(LCD)                                031f01df
DISPC_DEFAULT_COLOR(LCD)                           00000000
DISPC_TRANS_COLOR(LCD)                             00000000
DISPC_TIMING_H(LCD)                                04f02f1f
DISPC_TIMING_V(LCD)                                00700303
DISPC_POL_FREQ(LCD)                                00000000
DISPC_DIVISORo(LCD)                                00010004
DISPC_SIZE_MGR(LCD)                                031f01df
DISPC_DATA_CYCLE1(LCD)                             00000000
DISPC_DATA_CYCLE2(LCD)                             00000000
DISPC_DATA_CYCLE3(LCD)                             00000000
DISPC_CPR_COEF_R(LCD)                              00000000
DISPC_CPR_COEF_G(LCD)                              00000000
DISPC_CPR_COEF_B(LCD)                              00000000
DISPC_DEFAULT_COLOR(TV)                            00000000
DISPC_TRANS_COLOR(TV)                              00000000
DISPC_SIZE_MGR(TV)                                 00000000
DISPC_DEFAULT_COLOR(LCD2)                          00000000
DISPC_TRANS_COLOR(LCD2)                            00000000
DISPC_SIZE_MGR(LCD2)                               00000000
DISPC_DEFAULT_COLOR(LCD2)                          00000000
DISPC_TRANS_COLOR(LCD2)                            00000000
DISPC_TIMING_H(LCD2)                               00000000
DISPC_TIMING_V(LCD2)                               00000000
DISPC_POL_FREQ(LCD2)                               00000000
DISPC_DIVISORo(LCD2)                               00040001
DISPC_SIZE_MGR(LCD2)                               00000000
DISPC_DATA_CYCLE1(LCD2)                            00000000
DISPC_DATA_CYCLE2(LCD2)                            00000000
DISPC_DATA_CYCLE3(LCD2)                            00000000
DISPC_CPR_COEF_R(LCD2)                             00000000
DISPC_CPR_COEF_G(LCD2)                             00000000
DISPC_CPR_COEF_B(LCD2)                             00000000
DISPC_OVL_BA0(GFX)                                 10000000
DISPC_OVL_BA1(GFX)                                 10000000
DISPC_OVL_POSITION(GFX)                            00000000
DISPC_OVL_SIZE(GFX)                                031f01df
DISPC_OVL_ATTRIBUTES(GFX)                          32004099
DISPC_OVL_FIFO_THRESHOLD(GFX)                      04ff04f8
DISPC_OVL_FIFO_SIZE_STATUS(GFX)                    00000500
DISPC_OVL_ROW_INC(GFX)                             00007881
DISPC_OVL_PIXEL_INC(GFX)                           00000001
DISPC_OVL_PRELOAD(GFX)                             000004ff
DISPC_OVL_WINDOW_SKIP(GFX)                         00000000
DISPC_OVL_TABLE_BA(GFX)                            00000000
DISPC_OVL_BA0(VID1)                                7e2bab80
DISPC_OVL_BA1(VID1)                                7e2bab80
DISPC_OVL_POSITION(VID1)                           00190000
DISPC_OVL_SIZE(VID1)                               02d601df
DISPC_OVL_ATTRIBUTES(VID1)                         16a08018
DISPC_OVL_FIFO_THRESHOLD(VID1)                     07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID1)                   00000800
DISPC_OVL_ROW_INC(VID1)                            00000001
DISPC_OVL_PIXEL_INC(VID1)                          00000001
DISPC_OVL_PRELOAD(VID1)                            000007ff
DISPC_OVL_FIR(VID1)                                04000400
DISPC_OVL_PICTURE_SIZE(VID1)                       02d601df
DISPC_OVL_ACCU0(VID1)                              00000000
DISPC_OVL_ACCU1(VID1)                              00000000
DISPC_OVL_BA0_UV(VID1)                             00000000
DISPC_OVL_BA1_UV(VID1)                             00000000
DISPC_OVL_FIR2(VID1)                               04000400
DISPC_OVL_ACCU2_0(VID1)                            00000000
DISPC_OVL_ACCU2_1(VID1)                            00000000
DISPC_OVL_ATTRIBUTES2(VID1)                        00000000
DISPC_OVL_PRELOAD(VID1)                            000007ff
DISPC_OVL_BA0(VID2)                                7e410000
DISPC_OVL_BA1(VID2)                                7e410000
DISPC_OVL_POSITION(VID2)                           00000000
DISPC_OVL_SIZE(VID2)                               001801df
DISPC_OVL_ATTRIBUTES(VID2)                         1aa08018
DISPC_OVL_FIFO_THRESHOLD(VID2)                     07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID2)                   00000800
DISPC_OVL_ROW_INC(VID2)                            00000001
DISPC_OVL_PIXEL_INC(VID2)                          00000001
DISPC_OVL_PRELOAD(VID2)                            000007ff
DISPC_OVL_FIR(VID2)                                04000400
DISPC_OVL_PICTURE_SIZE(VID2)                       001801df
DISPC_OVL_ACCU0(VID2)                              00000000
DISPC_OVL_ACCU1(VID2)                              00000000
DISPC_OVL_BA0_UV(VID2)                             00000000
DISPC_OVL_BA1_UV(VID2)                             00000000
DISPC_OVL_FIR2(VID2)                               04000400
DISPC_OVL_ACCU2_0(VID2)                            00000000
DISPC_OVL_ACCU2_1(VID2)                            00000000
DISPC_OVL_ATTRIBUTES2(VID2)                        00000000
DISPC_OVL_PRELOAD(VID2)                            000007ff
DISPC_OVL_BA0(VID3)                                7e41c000
DISPC_OVL_BA1(VID3)                                7e41c000
DISPC_OVL_POSITION(VID3)                           02f00000
DISPC_OVL_SIZE(VID3)                               002f01df
DISPC_OVL_ATTRIBUTES(VID3)                         0ea08010
DISPC_OVL_FIFO_THRESHOLD(VID3)                     07ff07f8
DISPC_OVL_FIFO_SIZE_STATUS(VID3)                   00000800
DISPC_OVL_ROW_INC(VID3)                            00000001
DISPC_OVL_PIXEL_INC(VID3)                          00000001
DISPC_OVL_PRELOAD(VID3)                            000007ff
DISPC_OVL_FIR(VID3)                                04000400
DISPC_OVL_PICTURE_SIZE(VID3)                       002f01df
DISPC_OVL_ACCU0(VID3)                              00000000
DISPC_OVL_ACCU1(VID3)                              00000000
DISPC_OVL_BA0_UV(VID3)                             00000000
DISPC_OVL_BA1_UV(VID3)                             00000000
DISPC_OVL_FIR2(VID3)                               04000400
DISPC_OVL_ACCU2_0(VID3)                            00000000
DISPC_OVL_ACCU2_1(VID3)                            00000000
DISPC_OVL_ATTRIBUTES2(VID3)                        00000000
DISPC_OVL_PRELOAD(VID3)                            000007ff
DISPC_OVL_FIR_COEF_H_0(VID1)                       00800000
DISPC_OVL_FIR_COEF_H_1(VID1)                       0e7df601
DISPC_OVL_FIR_COEF_H_2(VID1)                       2172f102
DISPC_OVL_FIR_COEF_H_3(VID1)                       3762f001
DISPC_OVL_FIR_COEF_H_4(VID1)                       f24e4ef2
DISPC_OVL_FIR_COEF_H_5(VID1)                       f06237f6
DISPC_OVL_FIR_COEF_H_6(VID1)                       f17221fa
DISPC_OVL_FIR_COEF_H_7(VID1)                       f67d0efe
DISPC_OVL_FIR_COEF_HV_0(VID1)                      00800000
DISPC_OVL_FIR_COEF_HV_1(VID1)                      0e7df6fe
DISPC_OVL_FIR_COEF_HV_2(VID1)                      2172f1fa
DISPC_OVL_FIR_COEF_HV_3(VID1)                      3762f0f6
DISPC_OVL_FIR_COEF_HV_4(VID1)                      f24e4e00
DISPC_OVL_FIR_COEF_HV_5(VID1)                      f0623701
DISPC_OVL_FIR_COEF_HV_6(VID1)                      f1722102
DISPC_OVL_FIR_COEF_HV_7(VID1)                      f67d0e01
DISPC_OVL_CONV_COEF_0(VID1)                        00000000
DISPC_OVL_CONV_COEF_1(VID1)                        00000000
DISPC_OVL_CONV_COEF_2(VID1)                        00000000
DISPC_OVL_CONV_COEF_3(VID1)                        00000000
DISPC_OVL_CONV_COEF_4(VID1)                        00000000
DISPC_OVL_FIR_COEF_V_0(VID1)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID1)                       0000fe01
DISPC_OVL_FIR_COEF_V_2(VID1)                       0000fa02
DISPC_OVL_FIR_COEF_V_3(VID1)                       0000f601
DISPC_OVL_FIR_COEF_V_4(VID1)                       000000f2
DISPC_OVL_FIR_COEF_V_5(VID1)                       000001f6
DISPC_OVL_FIR_COEF_V_6(VID1)                       000002fa
DISPC_OVL_FIR_COEF_V_7(VID1)                       000001fe
DISPC_OVL_FIR_COEF_H2_0(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_1(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_2(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_3(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_4(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_5(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_6(VID1)                      00000000
DISPC_OVL_FIR_COEF_H2_7(VID1)                      00000000
DISPC_OVL_FIR_COEF_HV2_0(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_1(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_2(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_3(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_4(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_5(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_6(VID1)                     00000000
DISPC_OVL_FIR_COEF_HV2_7(VID1)                     00000000
DISPC_OVL_FIR_COEF_V2_0(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_1(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_2(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_3(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_4(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_5(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_6(VID1)                      00000000
DISPC_OVL_FIR_COEF_V2_7(VID1)                      00000000
DISPC_OVL_FIR_COEF_H_0(VID2)                       00800000
DISPC_OVL_FIR_COEF_H_1(VID2)                       0e7df601
DISPC_OVL_FIR_COEF_H_2(VID2)                       2172f102
DISPC_OVL_FIR_COEF_H_3(VID2)                       3762f001
DISPC_OVL_FIR_COEF_H_4(VID2)                       f24e4ef2
DISPC_OVL_FIR_COEF_H_5(VID2)                       f06237f6
DISPC_OVL_FIR_COEF_H_6(VID2)                       f17221fa
DISPC_OVL_FIR_COEF_H_7(VID2)                       f67d0efe
DISPC_OVL_FIR_COEF_HV_0(VID2)                      00800000
DISPC_OVL_FIR_COEF_HV_1(VID2)                      0e7df6fe
DISPC_OVL_FIR_COEF_HV_2(VID2)                      2172f1fa
DISPC_OVL_FIR_COEF_HV_3(VID2)                      3762f0f6
DISPC_OVL_FIR_COEF_HV_4(VID2)                      f24e4e00
DISPC_OVL_FIR_COEF_HV_5(VID2)                      f0623701
DISPC_OVL_FIR_COEF_HV_6(VID2)                      f1722102
DISPC_OVL_FIR_COEF_HV_7(VID2)                      f67d0e01
DISPC_OVL_CONV_COEF_0(VID2)                        00000000
DISPC_OVL_CONV_COEF_1(VID2)                        00000000
DISPC_OVL_CONV_COEF_2(VID2)                        00000000
DISPC_OVL_CONV_COEF_3(VID2)                        00000000
DISPC_OVL_CONV_COEF_4(VID2)                        00000000
DISPC_OVL_FIR_COEF_V_0(VID2)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID2)                       0000fe01
DISPC_OVL_FIR_COEF_V_2(VID2)                       0000fa02
DISPC_OVL_FIR_COEF_V_3(VID2)                       0000f601
DISPC_OVL_FIR_COEF_V_4(VID2)                       000000f2
DISPC_OVL_FIR_COEF_V_5(VID2)                       000001f6
DISPC_OVL_FIR_COEF_V_6(VID2)                       000002fa
DISPC_OVL_FIR_COEF_V_7(VID2)                       000001fe
DISPC_OVL_FIR_COEF_H2_0(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_1(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_2(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_3(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_4(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_5(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_6(VID2)                      00000000
DISPC_OVL_FIR_COEF_H2_7(VID2)                      00000000
DISPC_OVL_FIR_COEF_HV2_0(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_1(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_2(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_3(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_4(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_5(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_6(VID2)                     00000000
DISPC_OVL_FIR_COEF_HV2_7(VID2)                     00000000
DISPC_OVL_FIR_COEF_V2_0(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_1(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_2(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_3(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_4(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_5(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_6(VID2)                      00000000
DISPC_OVL_FIR_COEF_V2_7(VID2)                      00000000
DISPC_OVL_FIR_COEF_H_0(VID3)                       00800000
DISPC_OVL_FIR_COEF_H_1(VID3)                       0e7df601
DISPC_OVL_FIR_COEF_H_2(VID3)                       2172f102
DISPC_OVL_FIR_COEF_H_3(VID3)                       3762f001
DISPC_OVL_FIR_COEF_H_4(VID3)                       f24e4ef2
DISPC_OVL_FIR_COEF_H_5(VID3)                       f06237f6
DISPC_OVL_FIR_COEF_H_6(VID3)                       f17221fa
DISPC_OVL_FIR_COEF_H_7(VID3)                       f67d0efe
DISPC_OVL_FIR_COEF_HV_0(VID3)                      00800000
DISPC_OVL_FIR_COEF_HV_1(VID3)                      0e7df6fe
DISPC_OVL_FIR_COEF_HV_2(VID3)                      2172f1fa
DISPC_OVL_FIR_COEF_HV_3(VID3)                      3762f0f6
DISPC_OVL_FIR_COEF_HV_4(VID3)                      f24e4e00
DISPC_OVL_FIR_COEF_HV_5(VID3)                      f0623701
DISPC_OVL_FIR_COEF_HV_6(VID3)                      f1722102
DISPC_OVL_FIR_COEF_HV_7(VID3)                      f67d0e01
DISPC_OVL_CONV_COEF_0(VID3)                        00000000
DISPC_OVL_CONV_COEF_1(VID3)                        00000000
DISPC_OVL_CONV_COEF_2(VID3)                        00000000
DISPC_OVL_CONV_COEF_3(VID3)                        00000000
DISPC_OVL_CONV_COEF_4(VID3)                        00000000
DISPC_OVL_FIR_COEF_V_0(VID3)                       00000000
DISPC_OVL_FIR_COEF_V_1(VID3)                       0000fe01
DISPC_OVL_FIR_COEF_V_2(VID3)                       0000fa02
DISPC_OVL_FIR_COEF_V_3(VID3)                       0000f601
DISPC_OVL_FIR_COEF_V_4(VID3)                       000000f2
DISPC_OVL_FIR_COEF_V_5(VID3)                       000001f6
DISPC_OVL_FIR_COEF_V_6(VID3)                       000002fa
DISPC_OVL_FIR_COEF_V_7(VID3)                       000001fe
DISPC_OVL_FIR_COEF_H2_0(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_1(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_2(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_3(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_4(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_5(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_6(VID3)                      00000000
DISPC_OVL_FIR_COEF_H2_7(VID3)                      00000000
DISPC_OVL_FIR_COEF_HV2_0(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_1(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_2(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_3(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_4(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_5(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_6(VID3)                     00000000
DISPC_OVL_FIR_COEF_HV2_7(VID3)                     00000000
DISPC_OVL_FIR_COEF_V2_0(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_1(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_2(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_3(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_4(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_5(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_6(VID3)                      00000000
DISPC_OVL_FIR_COEF_V2_7(VID3)                      00000000

d/omapdss/dsi
DSI_REVISION                        00000040
DSI_SYSCONFIG                       00000015
DSI_SYSSTATUS                       00000001
DSI_IRQSTATUS                       00000180
DSI_IRQENABLE                       0015c000
DSI_CTRL                            000ae29f
DSI_COMPLEXIO_CFG1                  2a0003d4
DSI_COMPLEXIO_IRQ_STATUS            00000000
DSI_COMPLEXIO_IRQ_ENABLE            3ff07fff
DSI_CLK_CTRL                        a0306005
DSI_TIMING1                         ffff1000
DSI_TIMING2                         ffffffff
DSI_VM_TIMING1                      000480a3
DSI_VM_TIMING2                      04040307
DSI_VM_TIMING3                      03c00320
DSI_CLK_TIMING                      00001710
DSI_TX_FIFO_VC_SIZE                 13121110
DSI_RX_FIFO_VC_SIZE                 13121110
DSI_COMPLEXIO_CFG2                  00020000
DSI_RX_FIFO_VC_FULLNESS             00000000
DSI_VM_TIMING4                      00001c77
DSI_TX_FIFO_VC_EMPTINESS            1f1f1f1f
DSI_VM_TIMING5                      0000010a
DSI_VM_TIMING6                      01c8005a
DSI_VM_TIMING7                      000e000f
DSI_STOPCLK_TIMING                  00000080
DSI_VC_CTRL(0)                      20808d91
DSI_VC_TE(0)                        00000000
DSI_VC_LONG_PACKET_HEADER(0)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(0)       00000000
DSI_VC_SHORT_PACKET_HEADER(0)       00000000
DSI_VC_IRQSTATUS(0)                 00000004
DSI_VC_IRQENABLE(0)                 000000db
DSI_VC_CTRL(1)                      20808d81
DSI_VC_TE(1)                        00000000
DSI_VC_LONG_PACKET_HEADER(1)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(1)       00000000
DSI_VC_SHORT_PACKET_HEADER(1)       00000000
DSI_VC_IRQSTATUS(1)                 00000004
DSI_VC_IRQENABLE(1)                 000000db
DSI_VC_CTRL(2)                      20808d81
DSI_VC_TE(2)                        00000000
DSI_VC_LONG_PACKET_HEADER(2)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(2)       00000000
DSI_VC_SHORT_PACKET_HEADER(2)       00000000
DSI_VC_IRQSTATUS(2)                 00000000
DSI_VC_IRQENABLE(2)                 000000db
DSI_VC_CTRL(3)                      20808d81
DSI_VC_TE(3)                        00000000
DSI_VC_LONG_PACKET_HEADER(3)        00000000
DSI_VC_LONG_PACKET_PAYLOAD(3)       00000000
DSI_VC_SHORT_PACKET_HEADER(3)       00000000
DSI_VC_IRQSTATUS(3)                 00000000
DSI_VC_IRQENABLE(3)                 000000db
DSI_DSIPHY_CFG0                     1023111c
DSI_DSIPHY_CFG1                     42050e31
DSI_DSIPHY_CFG2                     b800000d
DSI_DSIPHY_CFG5                     fc000000
DSI_PLL_CONTROL                     00000018
DSI_PLL_STATUS                      00006383
DSI_PLL_GO                          00000000
DSI_PLL_CONFIGURATION1              0841381e
DSI_PLL_CONFIGURATION2              00656004

Best regards,

Anthony

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OMAP5 timing dispc timing relations