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Help on dual access explanation

Robert W
Mastermind 7100 points

Hi,

I want to know about dual access. I find the following article from spra215.pdf. The last sentence is difficult to understand. Could you explain it to me?

Thanks,

’C5x SARAM is NOT just one big RAM block where only one access

per cycle is allowed. Instead, it is actually made up of 2K-word size

independent RAM blocks, each one of which allows one CPU

access per cycle. Hence, the CPU can read/write one 2K block while

accessing another 2K block at the same time. All ’C5x processors

support multiple accesses to SARAM in one cycle as long as they

go to different RAM blocks. In the case where total SARAM size is

not a multiple of 2, one block is made smaller than 2K words.

  • 0
    Mastermind 7100 points

    Hi,

    I do not see any example code accessing DARAM yet.  Could you give me an example to utilize DARAM? Thanks

  • 0 in reply to Robert W
    TI__Genius 12575 points

    Hello Robert,

      In CSL example folder you could check on "CSL_DAT_Example_Out" example.

      Hope this helps.

    Regards

     Vasanth

  • 0 in reply to Vasantha K
    TI__Genius 12575 points

    Also regarding DARAM:

    The advantage of DARAM over SARAM is with performance:

    Each DARAM block can perform two accesses per cycle (two reads, two writes, or a read and a write). DARAM can be accessed by the internal program, data, or DMA buses.

    Hope this helps

    Regards

     Vasanth

  • 0 in reply to Vasantha K
    Mastermind 7100 points

    Thanks. Although the example does have DARAM used, I do not see what the advantage is in its use. It is only like a general RAM use from my first observation.

    Which part of the example has dual access? Could you give me a little more explanation?

  • 0 in reply to Robert W
    TI__Guru 64500 points

    Robert W said:

    Thanks. Although the example does have DARAM used, I do not see what the advantage is in its use. It is only like a general RAM use from my first observation.

    Yes, it is only RAM.  However, it is a RAM architecture that allows for 2 operations (accesses) to occur within the same clock cycle.  On the C5000 architecture, there multiple busses involved from the CPU alone, Program read, Data read, Data write, etc.  A dual-access RAM allows for up to 2 of those accesses to occur to the same memory block in a single clock cycle.

    The advantage is that you can accomplish more things in a clock cycle which leads to a performance gain.  Otherwise, in a Single-Access RAM (SARAM) only one of those operations would be allowed to be performed in a clock cycle to a particular memory block.  The other operations will be stalled until the next clock cycle, and so on and so on.

    Robert W said:

    Which part of the example has dual access? Could you give me a little more explanation?

    Having not looked at the example, look for operations that will occur in the same memory block at the same time.