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DM8148 EDMA3 Missing Transfer Completion

Elad Roichman
Intellectual 350 points

Hello,

I'm using the DM8148 SoC and running it under OPP166 (ARM running at 1 GHz and DSP running at 750 MHz).

I'm trying to use QDMA channels 2 and 3 on the DSP side using the EDMA3LLD driver (version 02.11.05.02) to copy data from / to DDR and the LL2.

No changes were made to the ARM / Linux code regarding the EDMA init / usage and it's based on TI EZSDK v5.05.02.00.

The EDMA configuration on the DSP side is as follows: configuring it as master on EDMA region 1 and initializing the DMA / QDMA channels, TCCs and PaRAM sets association based on the table below (taken from the following link: http://processors.wiki.ti.com/index.php/TI81XX_PSP_EDMA_Driver_User_Guide):

Present configuration of EDMA3 resources on DM814X platform:

EDMA3 ResourceDM814X
ARM DSP
DMA Channel 2-13, 16-25, 32-47, 52-55 0-1, 14-15, 26-31, 48-51, 56-63
QDMA Channel 0,1 2-7
TCC 2-13, 16-25, 32-47, 52-55 0-1, 14-15, 26-31, 48-51, 56-63
PaRAM Set 2-13, 16-25, 32-47, 52-55, 64-127 0-1, 14-15, 26-31, 48-51, 56-63, 128-511

My problem is as follows: after running the system, I'm able to see the QDMA transfers taking place. However, after a random period of time (usually a few seconds), the DSP is reaching an infinite loop (in my code) which polls the IPR register for the proper event (based on the last transfer).

Looking at the last PaRAM set associated with the last transfer, I saw that the transfer took place, but the transfer complete interrupt isn't set in the IPR for the transfer configured TCC).

I wasn't able to re-create the problem if I put breakpoints before initiating a transfer and before polling the IPR. Everytime I hit the pooling breakpiont, I could see the correct bit set in the IPR and the DSP continued its run.

What could be the cause for this problem? Could it be some sort of race condition between the ARM and the DSP?

Thanks in advance,

Elad.

  • 0
    TI__Guru**** 170625 points

    Elad,

    Elad Roichman said:
    I'm trying to use QDMA channels 2 and 3 on the DSP side using the EDMA3LLD driver (version 02.11.05.02) to copy data from / to DDR and the LL2.

    Are you aligned with the below user guide?

    http://processors.wiki.ti.com/index.php/Programming_the_EDMA3_using_the_Low-Level_Driver_%28LLD%29

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 350 points

    Hi Pavel,

    I verified that I'm aligned with the user guide. Eventually I fixed the problem as described below:

    1) Instead of defining 2 driver instances of EDMA (one for the EDMA channels and one for the QDMA channels), I use only one EDMA driver instance which controls both the EDMA and QDMA channels. I believe that my definition of the QDMA channels driver instance, which used EDMA region '0', conflicted with the Cortex A8 ARM.

    2) I changed the TCC field in the OPT field for my QDMA channels to match the TCCs owned by the DSP according to the table I posted in my original post.

    3) I perform polling for QDMA completion events on the correct EDMA region IPR register and I also clear the appropriate interrupts on the same register. Previously, I performed these operation on the general IPR register and not the specific region one.

    Thanks for the help anyway!

    Regards,

    Elad.