Multi-chip DDR timing

DDR timing spreadsheet: http://processors.wiki.ti.com/index.php/Programming_mDDR/DDR2_EMIF_on_OMAP-L1x/C674x

DDR Interface Drive Strength: http://processors.wiki.ti.com/index.php/DDR_Interface_Drive_Strength

DDR Routing Checklist: http://processors.wiki.ti.com/index.php/DDR_Routing_Checklist#DDR2.2FmDDR.2FDDR3_Routing_Checklist

None of the references includes the timing information I'm seeking - the number of nanoseconds or clock cycles before assertion of DDR_CS that the L-138 DDR address lines and bank select lines stabilize. In the absence of this information I will proceed on the assumption that the figure is 0.

I also must assume that the DDR_CS output is active only during times when the DDR2 RAM chips need it - during RAS, CAS and WE. I have observed that qualifying this signal with address and bank select signals results in discontinuities since the DDR chip latches an internal select signal in its Activate phase.

In order to develop an external address-qualified CS signal it will apparently be necessary to latch DDR_CS with a transparent latch. Such logic will have to be very fast in the absence of any positive address setup time. I am proceeding to design such logic using the TI 74AUC logic family and hope to report a positive outcome very soon.

It would appear that the OMAP designers never anticipated that more than one DDR chip would be used in an OMAP design. I expect to be able to demonstrate how to break this barrier.

Since the last posting I have discovered that large (2Gb) DDR2 chips are indeed available in the temperature ranges required for this product, so the rationale for using smaller chips has disappeared. \

Please disregard this thread. If necessary, please remove the post.