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DM368 DDR2 data signals swap

Champs,

 

I heard that some DDR2 controller support DDR2 data signals swapping between DQ[0:8] and DQ[9:15] to make PCB routing easier.

Does DM368 DDR2 controller support this DDR2 data signal swapping feature?

 

Quick reply will be appreciated because PCB layout is on going.

 

W.S. Yeo

  • after all what i've seen from TIs parts numbering its assumed by me that this device is very compatible with the DM365 - so you might have a look at the DDR2 interface data sheet of that SoC.

  • Was there any answer to this question if you could swap DDR2 data lines with each other in DQ[7:0] and also with each other in DQ[15:8]. I know that you can not swap data lines between low byte and high byte. TI documentation stated that the DDR2 controller is JEDEC compliant which means you could swap the data lines but it would be nice to have confirmation from TI that this is the case.

    Thanks.