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C6455 memory sections Linking problem

Surajkumar Mokhasi
Prodigy 200 points

Hi,

I have defined my memory mapping for C6455 as follows in the .cmd file,

MEMORY
{
L2RAM: o = 0x00800000 l = 0x000FFFFF /* 2MB L2 Internal SRAM */
L2DRAM: o = 0x00900000 l = 0x000FFFFF
L1PRAM: o = 0x00E00000 l = 0x00008000 /* 32kB L1 Program SRAM/CACHE */
L1DRAM: o = 0x00F00000 l = 0x00008000 /* 32kB L1 Data SRAM/CACHE */
EMIFA_CE2: o = 0xA0000000 l = 0x00800000 /* 8MB EMIFA CE2 */
EMIFA_CE3: o = 0xB0000000 l = 0x00800000 /* 8MB EMIFA CE2 */
EMIFA_CE4: o = 0xC0000000 l = 0x00800000 /* 8MB EMIFA CE2 */
EMIFA_CE5: o = 0xD0000000 l = 0x00800000 /* 8MB EMIFA CE2 */
DDR2_BANK1: o = 0xE0000000 l = 0x007FFFFF
DDR2_BANK2: o = 0xE0800000 l = 0x007FFFFF
DDR2_BANK3: o = 0xE1000000 l = 0x007FFFFF
DDR2_BANK4: o = 0xE1800000 l = 0x007FFFFF

}

then I have created sections for the memory as follows,


SECTIONS
{
.text > L2RAM
.stack > L2RAM
.bss > L2RAM
.cio > L2RAM
.const > L2RAM
.data > L2RAM
.switch > L2RAM
.sysmem > L2RAM
.far > L2RAM
.args > L2RAM
.ppinfo > L2RAM
.ppdata > L2RAM
L2_sram > L2RAM
L2_sram_data > L2DRAM
L1_code > L1PRAM
L1_data > L1DRAM

sdram_bank1 > DDR2_BANK1
sdram_bank2 > DDR2_BANK2
sdram_bank3 > DDR2_BANK3
sdram_bank4 > DDR2_BANK4

/* COFF sections */
.pinit > L2RAM
.cinit > L2RAM

/* EABI sections */
.binit > L2RAM
.init_array > L2RAM
.neardata > L2RAM
.fardata > L2RAM
.rodata > L2RAM
.c6xabi.exidx > L2RAM
.c6xabi.extab > L2RAM
}

Example of variable declaration in .c file:

#pragma DATA_SECTION (g_Var1,"L1_data")   (Placing the variable in L1_data section (i.e.) into L1 Data memory)

int g_Var1=0;

Problem:: The mapping and section definitions are fine, and the variables declared are placed into appropriate memory locations. But after compiling and loading the project on the DSK6455, the code execution is undetermined. Means to say that the functions written are not executed as expected.

Note: We are using "far" memory model.

Kindly suggest us if there are any project options to be changed. If so, then what are the changes?

  • 0
    TI__Guru* 84110 points

    Surajkumar,

    Do you really want to give up all of your L1P and L1D cache for use as SRAM? That is how you are allocating it in this linker command file.


    If that is the case, you will also need to make sure that you have turned off all the cache so the L1 and L2 memories are configured for only use as SRAM. The default is for L1 memories to be 100% cache and L2 100% SRAM.

    TI-RTOS has tools to make this easy to configure. There are also CSL functions to do this for you. If you are not using either of those, then you will need to write your own configuration functions to take care of these items, and it will need to be handled carefully.

    I recommend you use the defaults so you do not have to study the documents like the datasheet and the Megamodule User Guide to get the proper bit settings in the proper registers on the chip.

    To see if this is the problem, move all of your L1D and L1P allocations to L2 or external memory and re-build, then see if it runs better.

    Whether you will use the CSL or not, you should download and install it so you can look at the examples and its functions to understand how to implement those functions yourself. Or save yourself a lot of trouble and use the CSL.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 200 points

    Hi,

    I have tried running the code by disabling the Cache (L1P_CACHE & L1D_CACHE) in gel file as follows.

    *(int *)L1PCFG = 0;
    *(int *)L1PCC = 0;

    *(int *)L1DFG = 0;
    *(int *)L1DCC = 0;

    But still code execution is unpredictable.

    When Data & Code is mapped to L2 SRAM . code is working fine.

    Kindly suggest us what to be done for mapping the same to L1PRAM & L1DRAM correctly.

    Note: If variable x is mapped to L2 memory (add: 0x00800008) has been verified using map file. But when we browse the same variable in memory browser the address appears to be 0x00000000. (Seems to be some linking issue). Kindly suggest on this also.

    Regards,
    Surajkumar

  • 0 in reply to Surajkumar Mokhasi
    TI__Guru* 84110 points

    Surajkumar,

    I appears your thread is not answered. You may want to remove the Answered tag you placed on my previous post.

    There is not quite enough information to give you any specific answers.

    The only chance for answers will come from debug. CCS gives you very good tools to observe all the behavior. You can verify the cache registers have been changed the way you intended by examining them in the Registers View and the Memory Browser. You can use the Memory Browser and its color coding to help figure out any caching issues. You can step through your code and observe the changes at critical points.

    For any specific answers, you will have to provide some more specific information. But I am sure you will learn a lot from your debugging.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 200 points

    I have configure L1 Program  & L1 Data as 4KB cache and rest of the memory has been mapped to other variables and data. Code is working fine in emulation mode.

    Thank you.