Using steps from TRM (additionally enabling I2C0_CLKCTRL:in CM_WKUP)
21.3.15.1 Module Configuration Before Enabling the Module
1. Program the prescaler to obtain an approximately 12-MHz I2C module clock (I2C_PSC = x; this value is to be calculated and is dependent on the System clock frequency).
2. Program the I2C clock to obtain 100 Kbps or 400 Kbps (SCLL = x and SCLH = x; these values are to be calculated and are dependent on the System clock frequency).
3. Configure its own address (I2C_OA = x) - only in case of I2C operating mode (F/S mode).
4. Take the I2C module out of reset (I2C_CON:I2C_EN = 1).
Immediately after step 4 the AERR flag is set in the I2C0_IRQSTATUS_RAW register. I have tried configuring the FIFO thresholds before and after EN=1 and still the issue remains.
Does anyone have any experience with this and perhaps know how to correct the issue? It does not seem that this is a valid condition to begin a master I2C transmit from the CPU.
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