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AM3874 DQS signal

Michi Yama
Guru 10030 points
Other Parts Discussed in Thread: AM3874

Dear Sir,

I would like to know the DQS signal's role internal logic of AM3874.

I attached my customer's signal waveform. Please see the below.

As you know from the above waveform, this picture shows DQS has some small peak. on rising edge and falling edge.

Does this small peak influence to read the data from DDR3?  Is DQS signal used for making the timing of data latch in AM3874? or DQS si used for enabling the data  buffer?

Please advise me.

Best regards,

Michi

  • 0
    TI__Mastermind 43875 points

    This looks like you have badly impedance matched traces and what you are seeing are reflections.

    Do you have series resistors on your DQS lines? If so then try changing the value of the resistor to see if you can better impedance match the signals.

    Have you followed all the DDR layout rules?

    This behavior is not good and needs to be fixed for reliable DDR operation.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Guru 10030 points

    Dear Steve-san,

    Thank you for your reply.

    We understand that we should clean the DQS signl waveform.

    However I would like to know how DQS signal is used for DQ. Is DQS used for CLK for FF for DQ latch?

    Or is DQ used for enable for DQ latch?

    Please advise me again.

    Best regards,

    Michi 

  • 0 in reply to Michi Yama
    TI__Mastermind 43875 points

    Please refer to the JEDEC DDR3 specification for exact details of how the DDR signals are processed and why thy need to be as they are.

    BR,

    Steve