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PMU events in OMAP4

Chao11
Intellectual 335 points

Hi,

I'm using the linux perf tool that comes with the 3.4 tilt kernel on OMAP4460. According to the TRM, the PMU event 4 is "Data read or write operation that causes a cache access". PMU event 6 and 7 are "Data read/write architecturally executed". perf shows the number of event 4 almost doubles event 6+event 7. My program is running a dummy loop. So the mis-speculation of data read/write should be rare. So I expect event 4 to be close to event 6+event 7. Could some one helps me to explain this? Thank you!

  • 0
    TI__Mastermind 29520 points

    Hello Chao11,

    Sorry for delayed  answer.

    The PMU provides six counters to gather statistics about the operation of the processor and memory system. Each counter can count any of the events available in Cortex-A9. Upon counter overflow, PMU can generate an interrupt on its PMUIRQ output.


    This interrupt signal is mapped to the CTI TRIGIN[1] input and routed to a Cortex-A9 MPU interrupt controller input (MA_IRQ_54 for Cortex-A9 CPU0 PMU; MA_IRQ_55 for Cortex-A9 CPU1 PMU).

    I suggest you referring to following function in arch/arm/kernel/perf_event_v7.c file


    static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
                          [PERF_COUNT_HW_CACHE_OP_MAX]
                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
        [C(L1D)] = {
            /*
             * The performance counters don't differentiate between read
             * and write accesses/misses so this isn't strictly correct,
             * but it's the best we can do. Writes and reads get
             * combined.
             */
            [C(OP_READ)] = {
                [C(RESULT_ACCESS)]    = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
                [C(RESULT_MISS)]    = ARMV7_PERFCTR_L1_DCACHE_REFILL,
            },
            [C(OP_WRITE)] = {
                [C(RESULT_ACCESS)]    = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
                [C(RESULT_MISS)]    = ARMV7_PERFCTR_L1_DCACHE_REFILL,
            },
            [C(OP_PREFETCH)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
            },
        },
        [C(L1I)] = {
            [C(OP_READ)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = ARMV7_PERFCTR_L1_ICACHE_REFILL,
            },
            [C(OP_WRITE)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = ARMV7_PERFCTR_L1_ICACHE_REFILL,
            },
            [C(OP_PREFETCH)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
            },
        },
        [C(LL)] = {
            [C(OP_READ)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
            },
            [C(OP_WRITE)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
            },
            [C(OP_PREFETCH)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
            },
        },
        [C(DTLB)] = {
            [C(OP_READ)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = ARMV7_PERFCTR_DTLB_REFILL,
            },
            [C(OP_WRITE)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = ARMV7_PERFCTR_DTLB_REFILL,
            },
            [C(OP_PREFETCH)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
            },
        },
        [C(ITLB)] = {
            [C(OP_READ)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = ARMV7_PERFCTR_ITLB_REFILL,
            },
            [C(OP_WRITE)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = ARMV7_PERFCTR_ITLB_REFILL,
            },
            [C(OP_PREFETCH)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
            },
        },
        [C(BPU)] = {
            [C(OP_READ)] = {
                [C(RESULT_ACCESS)]    = ARMV7_PERFCTR_PC_BRANCH_PRED,
                [C(RESULT_MISS)]    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
            },
            [C(OP_WRITE)] = {
                [C(RESULT_ACCESS)]    = ARMV7_PERFCTR_PC_BRANCH_PRED,
                [C(RESULT_MISS)]    = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
            },
            [C(OP_PREFETCH)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
            },
        },
        [C(NODE)] = {
            [C(OP_READ)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
            },
            [C(OP_WRITE)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
            },
            [C(OP_PREFETCH)] = {
                [C(RESULT_ACCESS)]    = CACHE_OP_UNSUPPORTED,
                [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
            },
        },
    };

    After that, see file - arch/arm/kernel/perf_event.c

    Best regards,

    Yanko

  • 0 in reply to Yanko Todorov-XID
    Intellectual 335 points

    Thank you. I had read those files before. But I still don't understand what causes the difference in event 4 and event 6,7.