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DM8148 - NAND Flash memory configuration

HRi
Guru 10750 points


Hi,

I want to use 512MB NAND flash and have the last 16MB to be used by the FPGA for the 512MB I used two CS each configured to 256MB is there a way to exclude the last 16MB to be used by another CS? OK, I can configure the second CS to 128MB (to get 384MB) and configure the base address of the third CS to follow the 384MB but than I will lose some memory, is there another way to do that?

Thanks,

HR

  • 0
    TI__Genius 10180 points

    Hi HR, 

    Contrary to random-access devices (NOR flash, SRAM), NAND devices do not use the GPMC_A[27:0] address lines for the interface.  Given NAND devices work in page/block stream mode, the devices receive their address bits during an addressing sequence with the ALE pin asserted.  These address bits are programmed via the GPMC_NAND_ADDRESS_i register (where i = CS#).  Once this addressing phase is passed ---- and the page location identified --- all operations thereafter are streamed and the address becomes irrelevant.

    As a result, you can safely initialize NAND device CS size to a minimum of 16 MB, and then utilize the GPMC_NAND_ADDRESS_i register to specify the NAND Flash page address you want to interface to. Chapter 11.2.4.12.1 of the DM814x TRM provides detailed information on how the NAND devices interface should be setup.

    The FPGA can be mapped to the next available 16 MB GPMC CS address space.  Hence you will only need two CS for this purpose.

    Best,

    Shiou Mei

  • 0 in reply to Shiou Mei Huang
    Guru 10750 points

    Hi Shiou Mei,

    I assume that I will need three CS as the max CS size is 256MB and I want to use 512MB NAND Flash, one of the option's I was thinking is to define one CS for the first 256MB than the second one for 128MB and then set the 16MB Flash at the starting address of 384MB (Third CS), with this setup I will lose part of the NAND Flash,

    Thanks,

    HR

  • 0 in reply to HRi
    TI__Genius 10180 points

    Hi HR,

    The maximum CS size is used for random-access memory like NOR flash or SRAM.  NAND, on the other hand, is interfaced to via page/block stream mode, and the address bits are sent out via the GPMC_NAND_ADDRESS_i register instead of address lines GPMC_A[27:0].  These NAND flash address bits DO NOT HAVE TO CORRESPOND with the CS region address locations (i.e. you can access 0x00050000 using the address bits even when CS base address is 0x08000000).

    As long as correct address bits are placed inside the GPMC_NAND_ADDRESS_i register during the NAND address sequence, you can access the 512 MB NAND data array with a minimum NAND CS size of 16 MBytes. This is documented in Section 11.2.4.12.1.1 of the DM814x TRM.

    Best,

    Shiou Mei

  • 0 in reply to Shiou Mei Huang
    Guru 10750 points

    Hi Shiou Mei,

    OK, Thanks,

    HR