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IPC between two independent images on c6657

Javier Eroles
Intellectual 430 points

Hi everyone,

I am working with the C6657 platform, SYS/BIOS version and package 6_37_00_20, and CCS 5.1.1.00031.

I want to split my application in two images, one is in charge of acquisition and preprocessing of data, and the other one is in charge of decoding and transfer to a PC. Each image should work in a different core

My idea so far is using an IPC mechanism (e.g. Notify) to tell the second core the moment when the first core finish with its task. The examples provided by TI is a single image loaded in the two cores.

Is there any example of this kind of situation? i guess there should be an agree between both cores about where to store the IPC info related in the MSMC area and this should be reflected in the .cfg file

Thanks in advance

Javier Eroles

  • 0
    TI__Mastermind 32475 points

    Javier,

    There is no example that I am aware of but you should be able to do what you are thinking of.  There are a few things you have to be careful of.  Namely, for the shared memory regions, you will need to make sure that your two programs do not overlap one another.  Another words, you might need to split of DDR3 memory and/or MSMC RAM between the two programs.

    And yes, both programs need to agree on where the IPC shared region is.

    Judah

  • 0 in reply to judahvang
    Intellectual 430 points

    Thanks Judah for your answer.

    So far I established the IPC by manually running each program on each core. When the first program finishes, then it sends a notification to the second core. The second core received the notification and starts with its duties.

    The problem that I had now is on the input data for the second core. The output data of the first core is stored in the DDR3 (base address 0x80000000). What I should expect to be done by the second core is read the data starting from this position and so on, but it seems that the data is not properly read from the DDR3. Do you know if I need to make any DDR3 address translation from one core to the other core? How should I do it?

    Thanks

  • 0 in reply to Javier Eroles
    TI__Mastermind 32475 points

    Javier,

    When you say "but it seems that the data is not properly read from the DDR3", do you mean it reads that data but the data is incorrect?  Sounds like a cache problem to me?  I assume your data in DDR3 on first core is getting cached and when you read the data from second core, you are getting old stale data.  If this is the case, you need to do some cache operations on the data in first core before you notify the second core to start reading it.

    Judah

  • 0 in reply to judahvang
    Intellectual 430 points

    Thanks Judah!

    In the end I missed a wbinvL2 after copying data into the DDR3 (I was expecting only a wb before copying data, but anyway).

    Javier