Hi,
I have a UPP L138 and a FPGA interface.
The UPP port is configured in receive mode with following configuration
data width = 16bit
Data Burst length = 1024
Clock rate 75Mhz.
Single Data rate
No wait enabled
We use a ping pong scheme to receive data in using DMA.
I try to transfer 8k of data (1k each) from FPGA to OMAP using UPP.
I hav seen the interface works for 37.5Mhz. When I switch to 75mhz there are data errors (Data miss actually) in packet. I am not getting the whole 8k data but a lot lesser.... the 1st 1 to 3k seems to be fine.....
Inter burst gap is about 30ns....
I just tried increasing the inter burst gap to 2.6us.....@ 75Mhz..... in this scenario there is no data miss...
PLease let me know what is the issue....
what will be the minimum inter burst period required??
