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EMC issue due to vout[0]_clk - help

Dominic Boyle
Prodigy 40 points

Hello,


I am currently attempting to get a product through EMC class B radiated emissions conformance. Unfortunately I have quite a large peak which follows the frequency of vout[0]_clk.  I have a 22r series termination resistor close to the pin AD12 but this has little affect. There are two approaches open to me where I hope you can help;

1. Are there registers in the DM8148 so that I can have a play with the drive, and slew characteristics?

2. What is default output drive and impedance of this pin?

Your help here would be much appreciated.


Kind regards.

Dominic

  • 0
    TI__Mastermind 43875 points

    Dominic,

    I can't comment on the slew/drive, but also make sure that you have a solid ground reference plane adjacent to the clock signal and that the clock signal does not cross any ground or power plane splits.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 40 points

    Hi Steve,

    Thanks for getting back to me. This is standard best practice for layout of high speed signals which has been followed. There are two causes for this peak;

    1. Signal drive strength .

    2. Very fast Clock edges.

    I need the ability to manipulate the above for this clock. Most IO pins have registers to provide this capability, but I can't find any for vout[0]_clk on pin AD12.

    BR.

    Dominic

  • 0 in reply to Dominic Boyle
    TI__Mastermind 43875 points

    Just wanted to check :-) You would be surprised how many designers make this mistake, myself included many eons ago.

    I would expect all pins to have this control. Are the bit fields in the PADCONFIG registers labelled differently to other PADCONFIG registers in the TRM?

    BR,

    Steve

  • 0 in reply to Steve Clynes
    Prodigy 40 points

    Hi Steve,

    "I would expect all pins to have this control. Are the bit fields in the PADCONFIG registers labelled differently to other PADCONFIG registers in the TRM?"

    That is what I would have thought too, but I can't find anything!!!!! I have searched through sprug8e.pdf for everything possibly related to DVO2 port for slew, drive strength....  and I can find nothing :-(.

    Dominic

  • 0 in reply to Dominic Boyle
    TI__Mastermind 43875 points

    OK, check the PINCNT register for the pin you are interested in and try different settings in bit 19. Some IOs contain slew rate control but it is completely unsupported. PINCNT registers should be described in the datasheet.

    BR,

    Steve

  • 0 in reply to Steve Clynes
    TI__Guru**** 170625 points

    Dominic,

    I think this is PINCNTL176 register, at physical address 0x48140ABC. This PINCNTL176 has the below bits:

    [18] RXACTIVE - receiver/input enable. 0x0: receiver disable, 0x1: receiver enable

    In case you have silicon revision 2.1, you should check DM814x silicon errata, advisory Advisory 2.1.87 Control Module, Pin Configuration (PINCNTLx), 3.3 V Mode Operation: Reduction in Power-On Hours May Occur if the Input Receiver is Disabled

    [19] SLEWCTRL - Select between Faster or Slower Slew rate. 0x0: fast, 0x1: slow

    This bit is given as RESERVED, based on the below silicon errata:

    Advisory 2.1.88 Control Module, Pin Configuration (PINCNTLx): ROM Modifies Bit 19

    Check also the below silicon errata advisory:
    Advisory 3.0.24 HDVPSS VOUT[x]_CLK: Does Not Support Positive-Edge Clocking


    Best regards,
    Pavel