• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 361 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UPP burst to burst timing minimum

Rakesh Muralidharan
Expert 2810 points

Hi,

Sorry that i am reposting this query...

I have a UPP interface between L-138 and an FPGA.....

The UPP port is configured in receive mode with following configuration

data width = 16bit

Data Burst length = 1024

Clock  rate 75Mhz.

Single Data rate

No wait enabled

We use a ping pong scheme to receive data in using DMA.

I try to transfer 8k of data (1k  each) from FPGA to OMAP using UPP.

I hav seen the interface works for 37.5Mhz. When I switch to 75mhz there are data errors (Data miss actually) in packet. I am not getting the whole 8k data but a lot lesser.... the 1st 1 to 3k seems to be fine.....

Inter burst gap is about 30ns....

I just tried increasing the inter burst gap to 2.6us.....@ 75Mhz..... in this scenario there is no data miss...


PLease let me know what is the issue....

what will be the minimum inter burst period required??

  • 0
    TI__Mastermind 20790 points

    Rakesh,

    For Single Data Rate (SDR) Interleave Transmit Only
    UPCTL.CHN = 0 (single-channel mode)
    UPCTL.DRA = 0 (single data rate)
    UPCTL.MODE = 1 (transmit mode)
    UPCTL.SDRTXIL = 1 (enable SDR transmit interleave)
    UPCTL.DDRDEMUX = 0 (disable DDR interleave)

    The internal DMA controller always writes data in bursts of 64 bytes.
    However, DMA read operations have configurable burst size, which may be set per channel using the RDSIZEI and RDSIZEQ bits in the uPP threshold configuration register (UPTCR).

    UPTCR.value = 0;    //all values 0 for 64byte DMA bursts read / write