AM3359 SPI 1 TX RX

There is no way the SPI serial transmit/receive can be interrupted by other tasks. You have not said what software you are running, whether SPI mode is FIFO or DMA. Generally the only way to clear the TX/RX buffers would be to reset the SPI module.

Hi,

I'm using SPI in  FIFO ( examples given in SDK 1.1.0.3) on ICE AM3359

using CCS 5.2 IDE

How can I use SPI in DMA mode, can you please guide

Regards,

Bindu

I am moving this to the Starterware forum.

Hi Bindu,

You could refer the StarterWare example for EVM AM335x from the below link where the Slave device being used is Winbond W25Q64bv flash device. EDMA is being used for data transfer.

AM335X_StarterWare_02_00_01_01\examples\evmAM335x\mcspi_edma

Regards,

Jeethan

>This might be because the SPI communication is interrupted : Tx buffer  is transmitting, RX buffer is receiving interrupted by higher task(This higher task has to be with high priority)

If higher task is not accessing same SPI1 instance - its unlikely that lower priority task gets stuck on SPI1 interrupt poll.

We did have a similar situation in EtherCAT application and in this case both tasks were accessing SPI1 and same peripheral (during a corner case during state transition I think). We solved it by adding a reasonable timeout to register polling - it is always a good practice to prevent deadlocks.

Hi Pratheesh,

Yes, In New SDK release I could find the timeout implementation.

I guess, when we connect the Ethercat master the SPI communication is interrupted

And this observation was at the start time when we connect EtherCAT master, like the Ethercat master was interrupting the SPI Communication

was the same observation from your end?

Regards,

Bindu

Hey Bindu,

I am using the ethercat master (like the example) and the SPI0 with EDMA on the ICE-Board (because it´s connected on J12 pinheader).

At the beginning the function SpiFlashInit overrides my SPI setup, and then there was a wrong behavoir in the SPI

    else if( AM335X_BOARD_TYPE_ICE == boardType )
    {
        //McSPI instance 0 on ICE
        //SpiFlashInit(0);

Is that what you mean with "like the Ethercat master was interrupting the SPI Communication" ?

Hi Daniel,

No , I did not mean with explained scenario, but instead

I'm working on EtherCAT project from SDK 1.1.0.3

1) If Ethercat master interrupts in between SPI communication, As the TX or RX buffer communication is in between

2)Ethercat Master interrupts after or before SPI communication, Tx buffer or RX buffer had completed communication

My observation was with point 1.

Regards,

Bindu