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How to disable both L1 and L2 cache on AM335x

Other Parts Discussed in Thread: AM3352

We are using AM3352 on Linux environment. I would like to set both L1 and L2 cache disabled to confirm DDR3 access tolerance.
Could you please advise how to disable the cache and check the operation on Linux?

There are two parameter in .config file,’ CPU_ICACHE_DISABLE’ and ‘CPU_DCACHE_DISABLE’.
If the both parameters are set to ‘Y’, both L1 and L2 are disabled?

Best regards,
masa

  • Hi Masa,

    This is from the Kconfig files:

    Disable I-Cache (I-bit) (CPU_ICACHE_DISABLE)

    CONFIG_CPU_ICACHE_DISABLE:

    Say Y here to disable the processor instruction cache. Unless
    you have a reason not to or are unsure, say N.

    Symbol: CPU_ICACHE_DISABLE [=n]
    Type : boolean
    Prompt: Disable I-Cache (I-bit)
    Defined at arch/arm/mm/Kconfig:714
    Depends on: CPU_CP15 [=y] && !CPU_ARM610 [=n] && !CPU_ARM710 [=n] && !CPU_ARM720T [=n] && !CPU_ARM740T [=n] && !CPU_XSCALE [=n] && !CPU_XSC3 [=n]
    Location:
    -> System Type

    Disable D-Cache (C-bit) (CPU_DCACHE_DISABLE)

    CONFIG_CPU_DCACHE_DISABLE:

    Say Y here to disable the processor data cache. Unless
    you have a reason not to or are unsure, say N.

    Symbol: CPU_DCACHE_DISABLE [=n]
    Type : boolean
    Prompt: Disable D-Cache (C-bit)
    Defined at arch/arm/mm/Kconfig:721
    Depends on: CPU_CP15 [=y]
    Location:
    -> System Type

    These are both L1 caches.

    The L2 cache is by default 64K of RAM.

    Best regards,
    Miroslav

  • Thank you for your response.

    I also check CA8 technical manual. I believe that the symbol of CPU_ICACHE_DISABLE and CPU_DCACHE_DISABLE controls 'I bit' and 'C bit'. According to the manual, L2 is also disabled when the both I and D cache is disabled. So under this configuration, L2 of Sitara is also disabled and work as SRAM. 

    Could you please advise if my understanding is correct? If some kind of configuration setting is required to disable L2, I would like to know it.

    Best regards,

    masa

  • Yes, CPU_ICACHE_DISABLE and CPU_DCACHE_DISABLE do in fact control the 'I' and 'C' bits, so disabling them both means that the L2 will also be disabled.

    Best regards,
    Miroslav