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How to test the rate for PCIE between C6678

Hi TI engineer

         In our application we connect 2 C6678 with each other with PCI Express.One for RC,another for EP.When we test the rate ,we found some strange things.Data count is 32KB, transfer is performed by EDMA:

         1st test:C6678 A send data to C6678 B.The time from beginning to EDMA finish(get completion code) is about 1ms.

         2nd test:C6678 A send data to C6678 B. B poll the transfer,send data back to A immediatelly after getting datas.But we find that A has to wait for about 100ms to get the data back.

         I don't think the operation in DSP will cost so much time,so I'm not sure why this happens.I want to know that:

        1.Did the edma completion mean the PCIE data transfer over?

         2.Is there any error in our test design?

        3.If I want to test the correct rate of PCIE transfer,what is the best way?

       Thank you very much.

        

        

       

  • In general, you need to set PCIE to GEN2 with 2 lanes and use EDMA to get the best throughput. It should not take that long to transfer 32KB data. Do you use the GEL script to initialize the DSP core to run at 1.0 GHz?

    Regards, Eric

  • Hi Eric

           I can make sure DSP working in 1GHz, DSP is gen2 and we certainly use EDMA to do the work.

           But the most important issue I want to know is now we cannot make sure that PCIE transfer finished the same time as the EDMA got its completion code.And how can we get the rate correctly.

           Can you offer some suggestion for this? Thank you very much.

           Regards.

  • Not sure if you did this way,

    - First configure the EDMA channel

    - get timstamp A by TSCL/TSCH then trigger the EDMA transfer by setting ESR bit

    - Polling the IPR bit for the channel, if it is set, record the timestamp B

    The time spend  = B - A 

    Regards, Eric

  • Hi Eric:

              So you can make sure that once IPR is set, data should have been transfered to the target device?How does the master know data transfer completed?Is there any information returned in PCIE data-link level?

              Thank you.

  • PCIE write is posted transaction, which means it doesn't wait for a "done", no matter write is by CPU or EDMA. If the data must land to the remote side to be considered as write finishes, then what you measured is PCIE one-way write latency, not PCIE throughput. For the latency, it would be hundreds of nano-seconds to write 4-bytes, I don't have the exact number.

    Using EDMA, the data is sent to PCIE Tx buffer and IPR is set, which doesn't mean data landed at the remote side. As long as the Tx buffer is not full, you can continue increase EDMA write speed until you reaches the point EDMA has event miss (set in EMR register), this is the throughput you can maintain.

    Regards, Eric 

  • Hi Eric

            Thank you for your answer,I have understanded what you said. So if we want to test the average rate of large size transfer(so we can ignore the latency from data going out of Tx to landing in target memory).

            In this condition,if we start next EDMA  immediately after last EDMA ending, can we make sure that there will be no corrupt?

            If we count the whole time the transfer takes, then calculate rate by it.Does the result declare the transfer rate of the PCIE lane correctly?

            Regards

  •  In this condition,if we start next EDMA  immediately after last EDMA ending, can we make sure that there will be no corrupt? [Eric: Yes]

            If we count the whole time the transfer takes, then calculate rate by it.Does the result declare the transfer rate of the PCIE lane correctly [Eric: Yes]

    Regards, Eric