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10 MHz external clock input

Tobyn VanVeghten
Intellectual 700 points

My design utilizes a very stable 10 MHz reference clock as the main PLL clock source on the C6748.  However, I see the C6748 requires a 12 MHz minimum input clock.  Any suggestions on how I can multiply this input clock to meet the C6748 PLL requirements?

Thanks,

Tobyn

  • 0
    TI__Expert 4760 points

    Hi Tobyn,

    You need to use clock multipliers for that and make sure it is of the correct amplitude -- 1.2V at the output.

    Most of the Clock multipliers are comes up with 3.3V output, you need to use voltage divider resistor to bring down the voltage to 1.2V .Please refer the C6748 LCDK schematics for more details.

    You can check with TI for suitable clock multipliers

    http://www.ti.com/lsds/ti/clocks-timers/clock-generators-products.page

    Regards

    Antony

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