I use C6416 receiving large amounts of data through FIFO .
When FIFO reach half_full,EXT_IN4 is triggered, then start an EDMA reading 4KB data from FIFO to inter SRAM and disable this INT in the ISR.
Then this EDMA triggers EDMA_INT,I enable EXT_IN4 again in ISR.
But is appears that 4KB or 8KB data is missing in middle of these data occasionally. Missing data is the original data, like has never been visited.
How dose this happen? How to handle it?
