C64: handling two very near interrupts

There are two answers to your questions, first we can start with how the C64x reacts to interrupts coming in very quickly.

bbclgw said:

 If   the first EXT_INT4 rising edge comes at  the 0th cycle and the second  EXT_INT4 rising edge comes at  the 5th cycle ,how dose the C64's core handle?

if the EXT_INT4 is enabled ,how many times dose ISR happen?

I believe the answer to your question is within section 5.4 of SPRU732 which describes the interrupt process in detail.

To answer the question directly, based on the timing diagram in figure 5-4 of SPRU732 two interrupt events 5 cycles apart would generate two effective ISR executions, keeping in mind that there is propagation delay between when the event happens and the CPU receives the interrupt signal such that the first event would have already set and cleared the IFR flag bit before the second event made it in to set the IFR flag bit again. When the second event hits the CPU the CPU will already be in an interrupted state, and will not be accepting execution of a new interrupt until the current one has completed (or software forces interrupts enabled again with the GIE during the ISR), thus the second event will be queued up with the IFR flag.

If the two events were somehow closer together, say one cycle apart, than you would run into a situation where you would only get one effective ISR execution from the two very close events. Looking at the timing diagram mentioned above the IFR flag is set and than two cycles later cleared, thus if you had another event come in while the IFR was already set, the event would be dropped.

bbclgw said:

Similarly,  the second  EXT_INT4 rising edge comes at  the 10th ,15th ,20th cycle .... and so on.

These would act the same as if the two events were only 5 cycles apart, unless the ISR had already completed or had set the GIE bit to enable interrupts again, in which case instead of queueing up with the IFR bit the ISR would actually run again.

If you were to mean that you had several events coming in at 5 cycle intervals than only the first event would run until the first ISR completed or the GIE was set again, events received between when the first event started its ISR and the ISR completed or the GIE was set would be dropped.

For an alternate answer to your query, you may want to look at the GPIO spec for your part, using GPIO for external interrupts is well and good however the GPIO pins are generally slower reacting than what you describe, particularly if you are running a higher speed DSP. Essentially, chances are that it is impossible to generate interrupt events within 5 cycles of each other with GPIO interrupts.