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Stuck configuring DPLL_PER

Joe Kreidler
Prodigy 160 points


I am using the Clock Tree Tool to determine how to configure registers so I can output 24 MHz on fref_clk1_out.

I'm using the crystal input of 38.4 MHz and I have the AUXCLK1 mux set to PER_DPLL_SCRM_CLK. With these settings, the gate from the DPLL_PER is closed in CTT so I just have to get the DPLL_PER to output on the CLKOUTX2_M3 signal. However, I'm stuck here. I can't figure out how to configure the DPLL_PER to send a clock signal to CLKOUTX2_M3. I've tried changing multiple parameters for the DPLL_PER but no luck.

There is something I'm missing. Can anyone provide some suggestions?

Joe

  • 0
    TI__Guru**** 161600 points

    Hello Joe,

    You need to properly configure the DPLL_ABE & DPLL_PER in order to achieve 24 MHz on fref_clk1_out. In addition to your settings you need to follow the bellow:
    For DPLL_ABE :
      Follow the DPLL_ABE preferred settings from OMAP4460 TRM: Table 3-76. DPLL_ABE Preferred Settings for SYS_CLK = 38.4 MHz .  You need to set M = 750, N=0 and M3 = 1  & lock the DPLL_ABE in CTT.

    For DPLL_PER: 

    Follow the DPLL_PER preferred settings from OMAP4460 TRM: Table 3-53. DPLL_PER Preferred Settings for SYS_CLK = 38.4 MHz . Set M = 40, N = 1; here you need to set M3 = 4

    Set the divider AUXCLK1 to 16 (this is the last divider before you fref_clk1_out pin). 

    I am also attaching the register dump from my configuration of CTT 4604.DUMP_OMAP4.txt  (you need to rename the file to DUMP_OMAP4.rd2 before loading it in CTT)

    Best Regards,
    Yordan

  • 0 in reply to Yordan Kovachev
    Prodigy 160 points

    Yordan,

    I was able to take your register dump and load it into CTT and see the desired frequency at fref_clk1_out. I greatly appreciate your time and assistance. The data you provided got me over the hump and I can configure my system from this point.

    Thank you!

    Joe