EDMA3 operation in FIFO_Mode

JAE KYUNG KIM

Other Parts Discussed in Thread: TMS320C6747

Hi, I'm jkiset.

I'm test interface between DSP(TMS320C6747) and my own FPGA FIFO(EMIFA AsyncMode : WrSetup=1,WrStrobe=3,WrHold=1,RdSetup=1,RdStrobe=5,RdHold=1);

I confirmed that increased value is read step by step from FPGA FIFO to DSP Buffer.

But, EDMA3 FIFO_Address_Mode is always read zero.

My code is below...(hEdma, callback is predefined)

acnt = sizeof(unsigned short);

bcnt = 100;   //

BRCnt = bcnt;

srcbidx = (int)(acnt);

desbidx = (int)(acnt);

srccidx = ((int)acnt * (int)bcnt);

descidx = ((int)acnt * (int)bcnt);

EDMA3_DRV_requestChannel ( hEdma, &chId, &tcc, (EDMA3_RM_EventQueue)0, &callback, NULL);

EDMA3_DRV_setSrcParams ( hEdma, chId, (unsigned int)src, EDMA3_DRV_ADDR_MODE_FIFO, EDMA3_DRV_W16BIT);

EDMA3_DRV_setDestParams ( hEdma, chId, (unsigned int)dst, EDMA3_DRV_ADDR_MODE_INCR, EDMA3_DRV_W16BIT);

EDMA3_DRV_setSrcIndex ( hEdma, chId, srcbidx, srccidx);

EDMA3_DRV_setDestIndex ( hEdma, chId, desbidx, descidx);

EDMA3_DRV_setTransferParams ( hEdma, chId, acnt, bcnt, 1, BRCnt, EDMA3_DRV_SYNC_AB);

EDMA3_DRV_setOptField ( hEdma, chId, EDMA3_DRV_OPT_FIELD_TCINTEN, 1u);

EDMA3_DRV_setOptField ( hEdma, chId, EDMA3_DRV_OPT_FIELD_ITCINTEN, 1u);

EDMA3_DRV_enableTransfer( hEdma, chId, EDMA3_DRV_TRIG_MODE_MANUAL);

...

I don't know what's wrong.

Tell me the answer or example code.

Thanks...

over 12 years ago

0 RandyP over 12 years ago

TI__Guru* 84110 points

Jkiset,

You do not want to use the EDMA3 FIFO Addressing Mode. This does not help you with transferring data to/from a FIFO over the EMIFA bus. Do not use the FIFO Addressing Mode, also called the Constant Addressing Mode, with the C6747 EMIF bus.

Is there anything else wrong with your transfer, or you were just concerned that the bit was 0?

Regards,
RandyP

0 JAE KYUNG KIM over 12 years ago in reply to RandyP

Prodigy 20 points

Hi, RandyP!!!

Thanks for your reply.

I want to know why I can't use EDMA FIFO Adressing Mode over the EMIFA bus in TMS320C6747(FPGA FIFO --> DSP Buffer).

It will not operate structurally? Is there a remarkable document?

I would like to know the exact reason.

Thanks...

0 RandyP over 12 years ago in reply to JAE KYUNG KIM

TI__Guru* 84110 points

Is there something you are trying to do that you cannot do with the correct SAM=DAM=0 modes?

Generally, when one is trying to read/write with an external FIFO, there is a single address to which you want to write. This is done with the EDMA3 by setting the SRCxIDX or DSTxIDX fields to 0. There is no need for any other support.

Please refer to the EDMA3 User Guide's description of the SAM and DAM bit fields to see the 'remarkable document' telling you not to use the Constant Addressing Mode on the C6747. This is sprufl1c, page 76. If you have any questions about what that document is telling you about how to properly use the SAM and DAM bit fields, please let us know.

Regards,
RandyP

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EDMA3 operation in FIFO_Mode