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C6678 L2 SRAM and MSM SRAM

takahiro kusunoki
Prodigy 130 points

Hi Support Team

Please let me ask you the following questions.

We would like to only use L2 as SRAM and MSM SRAM, since we don't want to use DDR3.

(Q1) Can Keystone Multicore support our requirement?

(Q2) If yes, Does L1 keep the coherency for both L2 as SRAM and MSM SRAM when the software cares of it?

Best Regards,

Kusunoki

  • 0
    Guru 10750 points

    Hi Kusunoki,

    (Q1) - Yes, you can as long as all of your SW fits into this memory,

    (Q2) - The coherency is between L1 and L2, there is no coherency between L1/L2 and the MSMC,

    Thanks,

    HR

  • 0 in reply to HRi
    Prodigy 130 points

    Hi HR,

    Thank you for your reply.

    Let me confirm your answer just in case.

    (Q1) Does HW maintain the coherency between L1 and L2 even though we configure L2 as SRAM(not cache)?

    (Q2) Is the following understanding correct?

    When we use 6657, we can use 3MB as internal SRAM(1024KB(L2) x 2 + 1MB(MSM)) .

    * 1024KB is dedicated for each core

    * 1MB(MSM) is shared with 2 cores.

    When we would like to keep the coherency between L1 and MSM, Software has to maintain it.

    Best Regards,

    Kusunoki

  • 0 in reply to takahiro kusunoki
    Guru 10750 points

    Hi Kusunoki,

    Yes, you are correct, please note that core "0" can access the L2 of core "1" and vice versa,

    If you would like to set part of the MSMC to non cache, in case you will set L1D or/and L1C to cache than you have to move it to a global address and set the correct MAR bit's,

    Thanks,

    HR

  • 0 in reply to HRi
    Prodigy 130 points

    Hi HR

    Thank you for your prompt reply.

    I appreciate your help.

    Best Regards,

    Kusunoki