Could someone captue audio data from mcasp as master mode?

Could someone captue audio data from mcasp as master mode?

I try this mode,it's seem impossible.

We contact 12.288M OSC to AHCLK pin,we only config mcasp regs,and have not config codec regs(this means codec have not work). We can get 48K FS clock and 1.532M bit clock,but  FS clock  wave(I2S mode) seems DSP mode wave

some codes as below:

static int ti81xx_mca1_wm8978_hw_params(struct snd_pcm_substream *substream,

                                           struct snd_pcm_hw_params *params)

{

              fmt = (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS |

                  SND_SOC_DAIFMT_NB_IF);            //default

static void davinci_hw_param(struct davinci_audio_dev *dev, int stream)
{
int i, active_slots;
u32 mask = 0;

printk("davinci_hw_param\n");

active_slots = (dev->tdm_slots > 31) ? 32 : dev->tdm_slots;
for (i = 0; i < active_slots; i++)
mask |= (1 << i);

//if(DM8168_EX2000 == boardType)
{
mcasp_set_bits(dev->base + DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC); //separated TX RX clock 
}

//TX
mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
// AHCLKXE|15); 
AHCLKXE); 

mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKXCTL_REG,
// AHCLKRE|15); 
/*AHCLKRE|*/127); 

//RX

mcasp_clr_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
AHCLKRE); 

mcasp_set_bits(dev->base + DAVINCI_MCASP_AHCLKRCTL_REG,
127); 

static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)

{            

              case SND_SOC_DAIFMT_CBS_CFS:

                            printk("SND_SOC_DAIFMT_CBS_CFS \n");

                            /* codec is clock and frame slave */

                            mcasp_set_bits(base + DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE|0x07);

                            mcasp_set_bits(base + DAVINCI_MCASP_TXFMCTL_REG, AFSXE);

                            mcasp_set_bits(base + DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE|0x07);

                            mcasp_set_bits(base + DAVINCI_MCASP_RXFMCTL_REG, AFSRE);       

                            mcasp_set_bits(base + DAVINCI_MCASP_PDIR_REG, (0x2d << 26));  //orig:0x07<<26             

                            break;