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L1DSRAM acess time on 6678

jose carlos cazarin
Intellectual 550 points

Hello ,

I'm running a program where I'm doing an L1D acess once in a loop, i'm using the release build with optimization level 3 and measuring the acess time using the CSL api (  CSL_tscRead ).

Im doing this:

CSL_tscRead ();

data_1[i] = data_2[j];

CSL_tscRead ();

data_1 it's on the DDR3  and data_2 its on the L1DSRAM, both of them are uint8_T.

It's taking 25 ns to do the above operation. Since L1D can be acessed every cycle of the dsp (according to this thread  http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/135086/487011.aspx#487011 ), I expected this time to be much shorter, so  why is it taking so long to read the memory from the L1D? Or this time normal?

Thanks!

  • 0
    TI__Guru* 81335 points

    Hi Jose,

    Apologize for the delay. I was searching to know about CSL_tscRead() API, got below threads. For your reference,

    http://e2e.ti.com/support/dsp/tms320c6000_high_performance_dsps/f/112/t/11641.aspx

    http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/275943.aspx

    Thank you.

  • 0
    TI__Guru*** 125430 points

    Questions:

    1. Is 25ns an average time, i.e. are some of the samples taking a very short amount of time and others taking longer, but the overall time divided by overall samples comes out to 25ns/sample?  Or is it consistently 25ns for every single write?
    2. How is the cache configured and have you enabled cacheability of that region of memory?

    In general I wouldn't expect that code to execute indefinitely as single cycle accesses.  The writes to DDR3 go through a write buffer and once that write buffer fills then the CPU will stall until another slot opens.