Hello experts,
In sprufp4.pd C5505 I2S User's guide, CLKPOL is defined,
0：Receive data is sampled on the rising edge and transmit data shifted on the falling edge of the bit clock.
1：Receive data is sampled on the falling edge and transmit data shifted on the rising edge of the bit clock.
However in DSP format, this description seems reverse.
When setting 0, transmit starts the rising edge of the I2S Clock.
Is that Ok or something is wrong in the setting?
The setting is
CLKPOL = 0
FSPOL = 0,
(I2SSCTRL: 0x90D1)
Regards,
Nori Shinozaki